US-12628672-B2 - Semiconductor package

Abstract

A semiconductor package includes a frame having a first surface and a second surface, and including a wiring structure and a through-hole. The package further includes a first redistribution structure disposed on the first surface of the frame and including a first insulating layer and a first redistribution layer on the first insulating layer and connected to the wiring structure, a bridge die in the through-hole and having an interconnector, and an encapsulant surrounding the bridge die, and covering the second surface of the frame. The package further includes a second redistribution structure disposed on the encapsulant, and including a second insulating layer and a second redistribution layer on the second insulating layer and connected to the interconnector and the wiring structure, and a plurality of semiconductor chips disposed on the second redistribution structure, connected to the second redistribution layer, and electrically connected to each other through the interconnector.

Inventors

• Sangkyu Lee
• Doohwan Lee

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20220728

Priority Date

20211012

Claims (18)

1. 1 . A semiconductor package, comprising: a frame having a first surface and a second surface opposing each other, and including a wiring structure connecting the first and second surfaces, the frame having a through-hole; a first redistribution structure disposed on the first surface of the frame, and including a first insulating layer and a first redistribution layer disposed on the first insulating layer and connected to the wiring structure; a bridge die disposed in the through-hole and having an interconnector; an encapsulant surrounding the bridge die, and covering the second surface of the frame, the encapsulant having a substantially flat upper surface; a second redistribution structure disposed on the substantially flat upper surface of the encapsulant, and including a second insulating layer and a second redistribution layer disposed on the second insulating layer and connected to the interconnector and the wiring structure; and a plurality of semiconductor chips disposed on the second redistribution structure, and connected to the second redistribution layer, the plurality of semiconductor chips electrically connected to each other through the interconnector, wherein the first insulating layer includes at least one first insulating layer disposed on the first surface of the frame, and the second insulating layer includes a plurality of second insulating layers stacked on the substantially flat upper surface of the encapsulant, and a number of the at least one first insulating layer is smaller than a number of the plurality of second insulating layers.
2. 2 . The semiconductor package of claim 1 , wherein a thickness of each of the plurality of second insulating layers is smaller than a thickness of the at least one first insulating layer.
3. 3 . The semiconductor package of claim 1 , wherein a level of an upper surface of the bridge die is about equal to or higher than a level of the second surface of the frame.
4. 4 . The semiconductor package of claim 1 , wherein the bridge die includes a bonding pad disposed on an upper surface of the bridge die and connected to the interconnector, and the wiring structure has a wiring layer located on the second surface of the frame, the encapsulant has a first hole exposing the bonding pad and a second hole exposing a contact area of the wiring layer, and the second redistribution layer is disposed on the encapsulant and includes a redistribution pattern having a first via connected to the bonding pad through the first hole and a second via connected to the contact area through the second hole.
5. 5 . The semiconductor package of claim 1 , wherein the bridge die includes a semiconductor block, and the interconnector is disposed on an upper surface of the semiconductor block.
6. 6 . The semiconductor package of claim 5 , wherein the bridge die includes a through-via penetrating through the semiconductor block and connected to the interconnector, wherein the through-via is connected to the first redistribution layer on a lower surface of the bridge die.
7. 7 . A semiconductor package, comprising: a frame having a first surface and a second surface opposing each other, and including a wiring structure connecting the first and second surfaces, the frame having a through-hole; a first redistribution structure disposed on the first surface of the frame, and including a first insulating layer and a first redistribution layer disposed on the first insulating layer and connected to the wiring structure; a bridge die disposed in the through-hole and having an interconnector; an encapsulant surrounding the bridge die, and covering the second surface of the frame, the encapsulant having a substantially flat upper surface; a second redistribution structure disposed on the substantially flat upper surface of the encapsulant and including a second insulating layer and a second redistribution layer disposed on the second insulating layer and connected to the interconnector and the wiring structure; and a plurality of semiconductor chips disposed on the second redistribution structure, and connected to the second redistribution layer, the plurality of semiconductor chips electrically connected to each other through the interconnector, wherein the bridge die includes a first conductive bump disposed on an upper surface of the bridge die and connected to the interconnector, and a level of an upper surface of the first conductive bump is lower than a level of the substantially flat upper surface of the encapsulant, wherein the second redistribution layer includes a redistribution via connected to the upper surface of the first conductive bump.
8. 8 . The semiconductor package of claim 7 , wherein the upper surface of the first conductive bump is about 0.2 μm to about 5 μm lower than the level of the substantially flat upper surface of the encapsulant.
9. 9 . The semiconductor package of claim 7 , wherein the wiring structure has a wiring layer disposed on the second surface of the frame, the encapsulant has a first hole exposing a contact area of the wiring layer, and the second redistribution layer is connected to the contact area of the wiring layer through the first hole.
10. 10 . The semiconductor package of claim 9 , wherein the contact area of the wiring layer has a recessed area disposed at a lower level than another region of the wiring layer covered by the encapsulant.
11. 11 . The semiconductor package of claim 9 , wherein the second insulating layer is disposed on the substantially flat upper surface of the encapsulant, and includes a second hole exposing an upper surface region of the first conductive bump and a third hole exposing the contact area of the wiring layer, and the second redistribution layer includes a redistribution pattern disposed on the second insulating layer, the redistribution pattern including a first via connected to the first conductive bump through the second hole and a second via connected to the contact area through the third hole.
12. 12 . The semiconductor package of claim 7 , wherein the wiring structure includes a wiring layer disposed on the second surface of the frame and a second conductive bump disposed on the wiring layer, wherein a level of an upper surface of the second conductive bump is about equal to or lower than a level of the substantially flat upper surface of the encapsulant.
13. 13 . A semiconductor package, comprising: a lower redistribution structure having a lower insulating layer and a lower redistribution layer disposed on the lower insulating layer; a frame disposed on the lower redistribution structure, including a wiring structure connected to the lower redistribution layer, and having a through-hole; a bridge die disposed on the lower redistribution structure, in the through-hole, and including a semiconductor block and an interconnector disposed on an upper surface of the semiconductor block; an encapsulant surrounding the bridge die in the through-hole, extending onto a first surface of the frame, and having an upper surface; an upper redistribution structure disposed on the encapsulant and including an upper insulating layer and an upper redistribution layer disposed on the upper insulating layer and connected to the interconnector; and a plurality of semiconductor chips disposed on the upper redistribution structure, and connected to the upper redistribution layer, the plurality of semiconductor chips electrically connected to each other through the interconnector, wherein the bridge die includes a conductive bump disposed on an upper surface of the bridge die and connected to the interconnector, the conductive bump having an upper surface disposed at a level lower than a level of the upper surface of the encapsulant.
14. 14 . The semiconductor package of claim 13 , wherein the frame has an additional through-hole, wherein the semiconductor package further includes a capacitor chip disposed in the additional through-hole.
15. 15 . The semiconductor package of claim 14 , wherein the capacitor chip has an upper surface on which a plurality of contact pads are arranged, and the plurality of contact pads are respectively connected to the upper redistribution layer.
16. 16 . The semiconductor package of claim 13 , wherein a number of layers included in the lower insulating layer is greater than a number of layers included in the upper insulating layer, wherein a thickness of the lower insulating layer is smaller than a thickness of the upper insulating layer.
17. 17 . The semiconductor package of claim 13 , wherein the wiring structure has a wiring layer located on a second surface of the frame, the encapsulant has a first hole exposing a contact area of the wiring layer, and the contact area of the wiring layer has a recessed area disposed at a lower level than another area of the wiring layer covered by the encapsulant.
18. 18 . The semiconductor package of claim 17 , wherein the upper insulating layer is disposed on the upper surface of the encapsulant and includes a second hole exposing an upper surface region of the conductive bump and a third hole exposing the contact area of the wiring layer, and the upper redistribution layer includes a redistribution pattern disposed on the upper insulating layer and includes a first via connected to the conductive bump through the second hole and a second via connected to the contact area through the third hole.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0134870 filed on Oct. 12, 2021, and Korean Patent Application No. 10-2021-0143342 filed on Oct. 26, 2021, the disclosures of which are incorporated by reference herein in their entireties. TECHNICAL FIELD Embodiments of the present inventive concept relate to a semiconductor package. DISCUSSION OF RELATED ART In accordance with the rapid development of the electronics industry and the needs of users, electronic devices are being miniaturized and multifunctionalized. According to such a process, a semiconductor package including a plurality of semiconductor chips is utilized. Since interconnection between the plurality of semiconductor chips may not be guaranteed by the printed circuit board, the plurality of semiconductor chips may be connected by a separate interposer. SUMMARY Example embodiments provide a semiconductor package having a novel interposer structure. According to example embodiments, a semiconductor package includes a frame having a first surface and a second surface opposing each other, including a wiring structure connecting the first and second surfaces, and having a through-hole; a first redistribution structure disposed on the first surface of the frame and including a first insulating layer and a first redistribution layer disposed on the first insulating layer and connected to the wiring structure; a bridge die disposed in the through-hole and having an interconnector; an encapsulant surrounding the bridge die, extending onto the second surface of the frame, and having a substantially flat upper surface; a second redistribution structure disposed on the encapsulant, the second redistribution structure including a second insulating layer and a second redistribution layer disposed on the second insulating layer and connected to the interconnector and the wiring structure; and a plurality of semiconductor chips disposed on the second redistribution structure, connected to the second redistribution layer, and electrically connected to each other through the interconnector. According to example embodiments, a semiconductor package includes a lower redistribution structure having a lower insulating layer and a lower redistribution layer disposed on the lower insulating layer; a frame disposed on the lower redistribution structure, including a wiring structure connected to the lower redistribution layer, and having a through-hole; a bridge die disposed on the lower redistribution structure, in the through-hole, and including a semiconductor block and an interconnector disposed on an upper surface of the semiconductor block; an encapsulant surrounding the bridge die in the through-hole, extending onto an upper surface of the frame, and having a substantially flat upper surface; an upper redistribution structure disposed on the encapsulant and including an upper insulating layer and an upper redistribution layer disposed on the upper insulating layer and connected to the interconnector; and a plurality of semiconductor chips disposed on the upper redistribution structure, connected to the upper redistribution layer, and electrically connected to each other through the interconnector. According to example embodiments, a semiconductor package includes a lower redistribution structure having a lower insulating layer and a lower redistribution layer disposed on the lower insulating layer; a bridge die disposed on the lower redistribution structure and including a semiconductor block and an interconnector disposed on an upper surface of the semiconductor block; a plurality of conductive posts disposed around the bridge die, on the lower redistribution structure; an encapsulant disposed on the lower redistribution structure and having a substantially flat upper surface higher than upper surfaces of the bridge die and the plurality of conductive posts; an upper redistribution structure disposed on the encapsulant, including an upper insulating layer and an upper redistribution layer disposed on the upper insulating layer, the upper redistribution layer respectively connected to the interconnector of the bridge die and the plurality of conductive posts; and a plurality of semiconductor chips disposed on the upper redistribution structure, connected to the upper redistribution layer, and electrically connected to each other through the interconnector. BRIEF DESCRIPTION OF THE DRAWINGS The above and other features of the present inventive concept will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings, in which: FIG. 1 is a cross-sectional view schematically illustrating a semiconductor package according to an example embodiment; FIG. 2 is a plan view illustrating the semiconductor package of FIG. 1 taken along line I-I′ according to an example embodiment; FIG. 3 is a cross-sectional view illustrating an