US-12628673-B2 - Electronic package and substrate structure thereof

Abstract

An electronic package is provided, which includes a substrate structure and an electronic element and a passive element disposed on the substrate structure, where a die placement area and a functional area separated from each other are defined on a surface of a substrate body of the substrate structure, so that a routing layer is arranged with linear conductive traces with a smaller width in the die placement area, and a sheet-shaped circuit with a larger width and electrically connected to the linear conductive traces is arranged in the functional area, so as to reduce a metal area on the surface of the substrate body, thereby avoiding the problem of warpage caused by stress concentration in the die placement area.

Inventors

• Wan-Rou CHEN
• Yi-Wen Liu
• Hsiu-Jung Li
• Yi-Chen Chi
• Tsung-Li LIN

Assignees

• SILICONWARE PRECISION INDUSTRIES CO., LTD.

Dates

Publication Date

20260512

Application Date

20221208

Priority Date

20220120

Claims (18)

1. 1 . A substrate structure, comprising: a substrate body having a surface defined with a die placement area and a functional area separated from each other; and a routing layer including a plurality of linear conductive traces arranged in the die placement area and a plurality of sheet-shaped circuits arranged in the functional area and electrically connected to the plurality of linear conductive traces, wherein each of the linear conductive traces has a width less than a width of each of the sheet-shaped circuits; wherein one end of the plurality of linear conductive traces is formed with a plurality of electrical connection pads located in the die placement area, and the other end of the plurality of linear conductive traces is connected to the plurality of sheet-shaped circuits.
2. 2 . The substrate structure of claim 1 , wherein the substrate body has a thickness less than 500 micrometers.
3. 3 . The substrate structure of claim 2 , wherein the thickness of the substrate body is 300 micrometers.
4. 4 . The substrate structure of claim 1 , wherein one of the plurality of sheet-shaped circuits is connected to at least two of the plurality of linear conductive traces.
5. 5 . The substrate structure of claim 1 , wherein the routing layer is an outermost circuit layer of the substrate body.
6. 6 . The substrate structure of claim 1 , wherein the plurality of linear conductive traces are only located in the die placement area and are not formed outside the die placement area.
7. 7 . The substrate structure of claim 1 , wherein the width of each of the linear conductive traces is less than or equal to a width of each of the electrical connection pads, and the width of each of the electrical connection pads is less than the width of each of the sheet-shaped circuits.
8. 8 . The substrate structure of claim 1 , wherein each of the linear conductive traces is connected to each of the sheet-shaped circuits by an auxiliary circuit, and the auxiliary circuit is arranged outside the die placement area and the functional area, wherein the auxiliary circuit has a width less than or equal to the width of each of the linear conductive traces.
9. 9 . An electronic package, comprising the substrate structure of claim 1 ; an electronic element disposed on the die placement area and electrically connected to the plurality of linear conductive traces; and a passive element disposed on the functional area and electrically connected to the plurality of sheet-shaped circuits.
10. 10 . The electronic package of claim 9 , wherein the substrate body has a thickness less than 500 micrometers.
11. 11 . The electronic package of claim 9 , wherein the substrate body has a thickness of 300 micrometers.
12. 12 . The electronic package of claim 9 , wherein one of the plurality of sheet-shaped circuits is connected to at least two of the plurality of linear conductive traces.
13. 13 . The electronic package of claim 9 , wherein the routing layer is an outermost circuit layer of the substrate body.
14. 14 . The electronic package of claim 9 , wherein the plurality of linear conductive traces are only located in the die placement area and are not formed outside the die placement area.
15. 15 . The electronic package of claim 9 , wherein the width of each of the linear conductive traces is less than or equal to a width of each of the electrical connection pads, and the width of each of the electrical connection pads is less than the width of each of the sheet-shaped circuits.
16. 16 . The electronic package of claim 9 , wherein the electronic element is electrically connected to the plurality of electrical connection pads.
17. 17 . The electronic package of claim 9 , wherein the electronic element is electrically connected to the plurality of linear conductive traces via a plurality of conductive bumps.
18. 18 . The electronic package of claim 9 , wherein each of the linear conductive traces is connected to each of the sheet-shaped circuits by an auxiliary circuit, and the auxiliary circuit is arranged outside the die placement area and the functional area, wherein the auxiliary circuit has a width less than or equal to the width of each of the linear conductive traces.

Description

BACKGROUND 1. Technical Field The present disclosure relates to a semiconductor device, and more particularly, to an electronic package capable of reducing warpage and a substrate structure thereof. 2. Description of Related Art With the development of the electronic industry, today's electronic products have tended to be designed in the direction of being light, thin, small, and functionally diverse, and the semiconductor packaging technique has also developed different packaging types. In order to meet the high integration and miniaturization requirements of semiconductor devices, in addition to the traditional wire bonding semiconductor packaging technique, the industry mainly uses a flip chip method to improve a wiring density of a semiconductor device. FIG. 1A is a schematic cross-sectional view of a conventional flip-chip semiconductor package 1. As shown in FIG. 1A, a semiconductor chip 11 is first bonded onto electrical contact pads 10a of a package substrate 10 by a plurality of solder bumps 13, and then the solder bumps 13 are reflowed. Next, an underfill 14 is formed between the semiconductor chip 11 and the package substrate 10 to cover the solder bumps 13. At least one passive element 15 is usually disposed on the package substrate 10, and the passive element 15 is electrically connected to the plurality of solder bumps 13 (or a plurality of electrical contact pads 10a as shown in FIG. 1B) of the semiconductor chip 11 via a single sheet-shaped circuit 100 of the package substrate 10. Due to the electrical requirements between the passive element 15 and the semiconductor chip 11, a sheet-shaped circuit 100 having a wider width is required as a current path, otherwise the passive element 15 (e.g., a capacitor) cannot achieve the expected function. However, in the conventional semiconductor package 1, the sheet-shaped circuit 100 of the package substrate 10 is a large-area metal structure, which is subjected to temperature cycles or stress changes, such as passing through a reflow oven or going through tests such as dropping and other processes, the package substrate 10 is prone to uneven stress distribution due to differences (e.g., mismatches) in Coefficient of Thermal Expansion (CTE) in various regions of the surface, resulting in warpage. The warpage situation easily causes the plurality of solder bumps 13 to separate from the package substrate 10 (even breakages of the solder bumps 13 may occur), resulting in failure (such as disconnection) of the electrical connection between the semiconductor chip 11 and the package substrate 10, resulting in that a product is scraped and a product yield drops. Therefore, how to overcome the above-mentioned drawbacks of the prior art has become an urgent issue to be solved at present. SUMMARY In view of the various deficiencies of the prior art, the present disclosure provides a substrate structure, comprising: a substrate body having a surface defined with a die placement area and a functional area separated from each other; and a routing layer including a plurality of linear conductive traces arranged in the die placement area and a plurality of sheet-shaped circuits arranged in the functional area and electrically connected to the plurality of linear conductive traces, wherein each of the linear conductive traces has a width less than a width of each of the sheet-shaped circuits. The present disclosure also provides an electronic package, comprising the aforementioned substrate structure; an electronic element disposed on the die placement area and electrically connected to the plurality of linear conductive traces; and a passive element disposed on the functional area and electrically connected to the plurality of sheet-shaped circuits. In the aforementioned electronic package, the electronic element is electrically connected to the plurality of linear conductive traces via a plurality of conductive bumps. In the aforementioned electronic package and the substrate structure thereof, the substrate body has a thickness less than 500 micrometers. For example, the thickness of the substrate body is 300 micrometers. In the aforementioned electronic package and the substrate structure thereof, one of the plurality of sheet-shaped circuits is connected to at least two of the plurality of linear conductive traces. In the aforementioned electronic package and the substrate structure thereof, the routing layer is an outermost circuit layer of the substrate body. In the aforementioned electronic package and the substrate structure thereof, the plurality of linear conductive traces are only located in the die placement area and are not formed outside the die placement area. In the aforementioned electronic package and the substrate structure thereof, one end of the plurality of linear conductive traces is formed with a plurality of electrical connection pads located in the die placement area, and the other end is connected to the plurality of sheet-shaped circuits.