US-12628674-B2 - Semiconductor package

US12628674B2US 12628674 B2US12628674 B2US 12628674B2US-12628674-B2

Abstract

A semiconductor package includes a first lower redistribution layer, a first upper redistribution layer over the first lower redistribution layer, a first semiconductor chip between the first lower redistribution layer and the first upper redistribution layer, a first connection post spaced apart from the first semiconductor chip and connecting the first lower redistribution layer to the first upper redistribution layer, a first interposition layer on the first upper redistribution layer, a second interposition layer on the first interposition layer, a second lower redistribution layer on the second interposition layer, a second upper redistribution layer over the second lower redistribution layer, a second semiconductor chip between the second lower redistribution layer and the second upper redistribution layer, and a second connection post spaced apart from each other and connecting the second lower redistribution layer to the second upper redistribution layer.

Inventors

Seok Geun Ahn
HWANYOUNG CHOI

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20230306
Priority Date: 20220708

Claims (15)

1 . A semiconductor package comprising: a first lower redistribution layer; a first upper redistribution layer over the first lower redistribution layer; a first semiconductor chip between the first lower redistribution layer and the first upper redistribution layer; a first connection post spaced apart from the first semiconductor chip and connecting the first lower redistribution layer to the first upper redistribution layer; a first interposition layer on the first upper redistribution layer; a second interposition layer on the first interposition layer; a second lower redistribution layer on the second interposition layer; a second upper redistribution layer over the second lower redistribution layer; a second semiconductor chip between the second lower redistribution layer and the second upper redistribution layer; and a second connection post spaced apart from the second semiconductor chip and connecting the second lower redistribution layer to the second upper redistribution layer, wherein: the first connection post vertically overlaps the second semiconductor chip, and the second connection post vertically overlaps the first semiconductor chip.
2 . The semiconductor package of claim 1 , further comprising: a first die attach film (DAF) in contact with a bottom surface of the first semiconductor chip and a top surface of the first lower redistribution layer; and a second die attach film (DAF) in contact with a top surface of the second semiconductor chip and a bottom surface of the second upper redistribution layer.
3 . The semiconductor package of claim 1 , wherein: the first semiconductor chip includes a plurality of first semiconductor chips, the semiconductor package further includes a plurality of additional first connection posts that are spaced apart from the plurality of first semiconductor chips and that connect the first lower redistribution layer to the first upper redistribution layer, the second semiconductor chip includes a plurality of second semiconductor chips, and the semiconductor package further includes a plurality of additional second connection posts that are spaced apart from the plurality of second semiconductor chips and that connect the second lower redistribution layer to the second upper redistribution layer.
4 . The semiconductor package of claim 1 , further comprising a solder ball connected to the first lower redistribution layer.
5 . The semiconductor package of claim 1 , further comprising a first chip post that connects the first semiconductor chip to the first upper redistribution layer.
6 . The semiconductor package of claim 5 , further comprising a second chip post that connects the second semiconductor chip to the second lower redistribution layer.
7 . The semiconductor package of claim 5 , wherein: the first chip post includes copper, each of the first interposition layer and the second interposition layer includes a conductive structure and an interposition dielectric layer that surrounds the conductive structure, the conductive structure includes copper, and the interposition dielectric layer includes an inorganic dielectric material.
8 . The semiconductor package of claim 1 , wherein each of the first lower redistribution layer, the first upper redistribution layer, the second lower redistribution layer, and the second upper redistribution layer includes a redistribution pattern and a redistribution dielectric layer that surrounds the redistribution pattern, wherein the redistribution dielectric layer includes a photosensitive dielectric material.
9 . A semiconductor package comprising: a first lower redistribution layer; a first upper redistribution layer on the first lower redistribution layer; a first semiconductor chip between the first lower redistribution layer and the first upper redistribution layer; a first interposition layer on the first upper redistribution layer; a second interposition layer on the first interposition layer; a second lower redistribution layer on the second interposition layer; a second upper redistribution layer on the second lower redistribution layer; and a second semiconductor chip between the second lower redistribution layer and the second upper redistribution layer, a first connection post that connects the first lower redistribution layer to the first upper redistribution layer; and a second connection post that connects the second lower redistribution layer to the second upper redistribution layer, wherein each of the first lower redistribution layer, the first upper redistribution layer, the second lower redistribution layer, and the second upper redistribution layer includes a redistribution pattern and a redistribution dielectric layer that surrounds the redistribution pattern, wherein the redistribution dielectric layer includes a photosensitive dielectric material, wherein the first connection post vertically overlaps the second semiconductor chip, and wherein the second connection post vertically overlaps the first semiconductor chip.
10 . The semiconductor package of claim 9 , further comprising a first chip post that connects the first semiconductor chip to the first upper redistribution layer, wherein the first chip post is between the first semiconductor chip and the first upper redistribution layer.
11 . The semiconductor package of claim 10 , wherein the first chip post includes copper.
12 . The semiconductor package of claim 10 , further comprising a second chip post that connects the second semiconductor chip to the second lower redistribution layer, wherein the second chip post is between the second semiconductor chip and the second lower redistribution layer.
13 . The semiconductor package of claim 9 , further comprising: a first die attach film in contact with a bottom surface of the first semiconductor chip and a top surface of the first lower redistribution layer; and a second die attach film in contact with a top surface of the second semiconductor chip and a bottom surface of the second upper redistribution layer.
14 . The semiconductor package of claim 9 , wherein each of the first interposition layer and the second interposition layer includes a conductive structure and an interposition dielectric layer that surrounds the conductive structure, wherein the conductive structure includes copper, and wherein the interposition dielectric layer includes an inorganic dielectric material.
15 . A semiconductor package comprising: a solder ball; a first lower redistribution layer on the solder ball; a first die attach film on the first lower redistribution layer; a first semiconductor chip on the first die attach film; a first molding layer on the first semiconductor chip; a first upper redistribution layer on the first molding layer; a first connection post that connects the first lower redistribution layer to the first upper redistribution layer; a first chip post that connects the first semiconductor chip to the first upper redistribution layer; a first interposition layer on the first upper redistribution layer; a second interposition layer on the first interposition layer; a second lower redistribution layer on the second interposition layer; a second molding layer on the second lower redistribution layer; a second semiconductor chip on the second molding layer; a second die attach film on the second semiconductor chip; a second upper redistribution layer on the second die attach film; a second connection post that connects the second lower redistribution layer to the second upper redistribution layer; and a second chip post that connects the second semiconductor chip to the second lower redistribution layer, wherein the first connection post vertically overlaps the second semiconductor chip, and wherein the second connection post vertically overlaps the first semiconductor chip.

Description

CROSS-REFERENCE TO RELATED APPLICATION This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2022-0084484 filed on Jul. 8, 2022 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. BACKGROUND The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a connection post and an interposition layer. In response to the rapid development of the electronic industry and user demands, electronic products have become smaller and increasingly multifunctional. There are also increased needs for miniaturization and multi-functionality of semiconductor devices used for electronic products. Recently, packages have been developed in which semiconductor chips are stacked to increase storage capacity and data process speeds. Such packages are required to densely stack the semiconductor chips. SUMMARY It is an aspect to provide a semiconductor package with increased reliability and improved electrical properties. According to an aspect of some embodiments, a semiconductor package may comprise: a first lower redistribution layer; a first upper redistribution layer over the first lower redistribution layer; a first semiconductor chip between the first lower redistribution layer and the first upper redistribution layer; a first connection post spaced apart from the first semiconductor chip and connecting the first lower redistribution layer to the first upper redistribution layer; a first interposition layer on the first upper redistribution layer; a second interposition layer on the first interposition layer; a second lower redistribution layer on the second interposition layer; a second upper redistribution layer over the second lower redistribution layer; a second semiconductor chip between the second lower redistribution layer and the second upper redistribution layer; and a second connection post spaced apart from each other and connecting the second lower redistribution layer to the second upper redistribution layer. According to another aspect of some embodiments, a semiconductor package may comprise: a first lower redistribution layer; a first upper redistribution layer on the first lower redistribution layer; a first semiconductor chip between the first lower redistribution layer and the first upper redistribution layer; a first interposition layer on the first upper redistribution layer; a second interposition layer on the first interposition layer; a second lower redistribution layer on the second interposition layer; a second upper redistribution layer on the second lower redistribution layer; and a second semiconductor chip between the second lower redistribution layer and the second upper redistribution layer. Each of the first lower redistribution layer, the first upper redistribution layer, the second lower redistribution layer, and the second upper redistribution layer may include a redistribution pattern and a redistribution dielectric layer that surrounds the redistribution pattern. The redistribution dielectric layer may include a photosensitive dielectric material. According to yet another aspect of some embodiments, a semiconductor package may comprise: a solder ball; a first lower redistribution layer on the solder ball; a first die attach film on the first lower redistribution layer; a first semiconductor chip on the first die attach film; a first molding layer on the first semiconductor chip; a first upper redistribution layer on the first molding layer; a first connection post that connects the first lower redistribution layer to the first upper redistribution layer; a first chip post that connects the first semiconductor chip to the first upper redistribution layer; a first interposition layer on the first upper redistribution layer; a second interposition layer on the first interposition layer; a second lower redistribution layer on the second interposition layer; a second molding layer on the second lower redistribution layer; a second semiconductor chip on the second molding layer; a second die attach film on the second semiconductor chip; a second upper redistribution layer on the second die attach film; a second connection post that connects the second lower redistribution layer to the second upper redistribution layer; and a second chip post that connects the second semiconductor chip to the second lower redistribution layer. The first connection post may vertically overlap the second semiconductor chip. The second connection post may vertically overlap the first semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A illustrates a cross-sectional view showing a semiconductor package according to some embodiments. FIG. 1B illustrates an enlarged view showing section A of FIG. 1A. FIG. 1C illustrates a top view showing the semiconductor package depicted in FIG. 1A. FIGS. 2A, 2B, 2C, 2D, 2E, and 2F illustrate cr