US-12628676-B2 - Device and method of very high density routing used with embedded multi-die interconnect bridge

US12628676B2US 12628676 B2US12628676 B2US 12628676B2US-12628676-B2

Abstract

A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.

Inventors

Robert Alan May
Wei-Lun Kane Jen
Jonathan L. Rosch
Islam A Salama
Kristof Darmawikarta

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260512
Application Date: 20240408

Claims (20)

1 . A semiconductor device, comprising: alternating layers of dielectric material and metal; a bridge die above the alternating layers of dielectric material and metal; a plurality of conductive pillars adjacent to sides of the bridge die; a first insulating layer above the alternating layers of dielectric material and metal, the first insulating layer laterally between the plurality of conductive pillars and the bridge die; a second insulating layer over the first insulating layer, over and in direct contact with an uppermost surface of the plurality of conductive pillars, and over the bridge die, the second insulating layer having a bottommost surface; a plurality of vias in the second insulating layer, the plurality of vias coupled to the plurality of conductive pillars and to the bridge die, wherein the plurality of vias have a bottommost surface at a same level as the bottommost surface of the second insulating layer; a first die coupled to the bridge die and to the plurality of conductive pillars; a second die coupled to the bridge die and to the plurality of conductive pillars; and a third insulating layer over the second insulating layer, the third insulating layer intervening between the second insulating layer and the first die.
2 . The semiconductor device of claim 1 , wherein one of the plurality of vias is offset from a central vertical access of a corresponding one the plurality of conductive pillars.
3 . The semiconductor device of claim 1 , wherein the plurality of vias is electrically connected to the plurality of conductive pillars and to the bridge die.
4 . The semiconductor device of claim 1 , wherein a first portion of the plurality of vias coupled to the plurality of conductive pillars has a pitch greater than a pitch of a second portion of the plurality of vias coupled to the bridge die.
5 . The semiconductor device of claim 1 , wherein the first die is a CPU die, and the second die is a memory die.
6 . The semiconductor device of claim 1 , wherein the first die is a first CPU die, and the second die is a second CPU die.
7 . The semiconductor device of claim 1 , wherein the first die is a first memory die, and the second die is a second memory die.
8 . The semiconductor device of claim 1 , wherein the first die and the second die are electrically coupled to the bridge die and to the plurality of conductive pillars.
9 . A semiconductor device, comprising: a first metal layer; a first dielectric material layer above the first metal layer; a second metal layer above the first dielectric material layer; a second dielectric material layer above the second metal layer; a bridge die above the second dielectric material layer; first and second conductive pillars adjacent to a first side of the bridge die; third and fourth conductive pillars adjacent to a second side of the bridge die, the second side laterally opposite to the first side; a first insulating layer above the second dielectric material layer, the first insulating layer laterally between the first and second conductive pillars, laterally between the second conductive pillar and the bridge die, laterally between the bridge die and the third conductive pillar, and laterally between the third and fourth conductive pillars; a second insulating layer over the first insulating layer, over and in direct contact with an uppermost surface of the first conductive pillar, over and in direct contact with an uppermost surface of the second conductive pillar, over and in direct contact with an uppermost surface of the third conductive pillar, and over and in direct contact with an uppermost surface of the fourth conductive pillar, and over the bridge die, the second insulating layer having a bottommost surface; vias in the second insulating layer, the vias coupled to the first, second, third and fourth conductive pillars and to the bridge die, wherein the vias have a bottommost surface at a same level as the bottommost surface of the second insulating layer; a first die electrically coupled to the bridge die and to the first and second conductive pillars; a second die electrically coupled to the bridge die and to the third and fourth conductive pillars; and a third insulating layer over the second insulating layer, the third insulating layer intervening between the second insulating layer and the first die.
10 . The semiconductor device of claim 9 , wherein one of the vias is coupled to and offset from a central vertical access of the third conductive pillar.
11 . The semiconductor device of claim 9 , wherein a first portion of the vias coupled to the first, second, third and fourth conductive pillars has a pitch greater than a pitch of a second portion of the vias coupled to the bridge die.
12 . The semiconductor device of claim 9 , wherein the first die is a first CPU die, and the second die is a second CPU die.
13 . A method of fabricating a semiconductor device, the method comprising: forming alternating layers of dielectric material and metal; providing a bridge die above the alternating layers of dielectric material and metal; forming a plurality of conductive pillars adjacent to sides of the bridge die; forming a first insulating layer above the alternating layers of dielectric material and metal, the first insulating layer laterally between the plurality of conductive pillars and the bridge die; forming a second insulating layer over the first insulating layer, over and in direct contact with an uppermost surface of the plurality of conductive pillars, and over the bridge die, the second insulating layer having a bottommost surface; forming a plurality of vias in the second insulating layer, the plurality of vias coupled to the plurality of conductive pillars and to the bridge die, wherein the plurality of vias have a bottommost surface at a same level as the bottommost surface of the second insulating layer; coupling a first die to the bridge die and to the plurality of conductive pillars; coupling a second die to the bridge die and to the plurality of conductive pillars; and forming a third insulating layer over the second insulating layer, the third insulating layer intervening between the second insulating layer and the first die.
14 . The method of claim 13 , wherein one of the plurality of vias is offset from a central vertical access of a corresponding one the plurality of conductive pillars.
15 . The method of claim 13 , wherein the plurality of vias is electrically connected to the plurality of conductive pillars and to the bridge die.
16 . The method of claim 13 , wherein a first portion of the plurality of vias coupled to the plurality of conductive pillars has a pitch greater than a pitch of a second portion of the plurality of vias coupled to the bridge die.
17 . The method of claim 13 , wherein the first die is a CPU die, and the second die is a memory die.
18 . The method of claim 13 , wherein the first die is a first CPU die, and the second die is a second CPU die.
19 . The method of claim 13 , wherein the first die is a first memory die, and the second die is a second memory die.
20 . The method of claim 13 , wherein the first die and the second die are electrically coupled to the bridge die and to the plurality of conductive pillars.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/091,048, filed Dec. 29, 2022, which is a continuation of pending U.S. patent application Ser. No. 17/888,177, filed Aug. 15, 2022, which is a continuation of U.S. patent application Ser. No. 16/322,423, filed on Jan. 31, 2019, now U.S. Pat. No. 11,508,662, issued Nov. 22, 2022, which is a U.S. National Stage Filing under 35 U.S.C. 371 from International Application No. PCT/US2016/054739 filed Sep. 30, 2016 and published in English as WO 2018/063316 on Apr. 5, 2018, the entire contents of which are hereby incorporated by reference herein. TECHNICAL FIELD Embodiments pertain to electronic packages. Some embodiments relate to high density routing used in conjunction with an embedded multi-die interconnect bridge (bridge) in electronic packages. BACKGROUND The electronics industry has continued to face an ever-increasing demand for faster and more powerful processing capacity, as well as increased storage capacity to feed the continuous hunger for faster devices and data rates. Electronic packages contain a wide variety integrated circuits (ICs), dies connected to substrates, and electronic structures of a disparate array of electronic products. Examples of these products include communication devices (e.g., smart phones), computers (e.g., laptops, tablets), vehicular devices, game devices, etc. Increasing miniaturization of ICs, and IC structures to increase the processing power has led to power management and interference issues with the consequent increase in interconnect density within the structures and between dies in an electronics package. One technology to provide dense interconnect routing between dies is an Embedded (Multi-die) Interconnect Bridge. However, due to current fabrication techniques and inherent properties of the dielectric material used to create the bridge, the use of a bridge may result in lossy and capacitive structures. Current bridge-based designs and fabrication techniques may lack flexibility and limit the number of bridge die in a single substrate and use to die having a 55 μm bump pitch of input/output (I/O) bumps on the die. It would be desirable to enable further miniaturization by providing a bridge with enhanced scalability that is capable of connecting to die having smaller bump pitches (e.g., 40 μm) without requiring a costly Si bridge re-design to implement. BRIEF DESCRIPTION OF THE FIGURES In the figures, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The figures illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. FIGS. 1A-1H illustrate cross-sectional views of a fabrication process using a bridge and very high density (VHD) routing using a substrate with a monolithic core in accordance with some embodiments. FIGS. 2A-2L illustrate cross-sectional views of a fabrication process using a bridge and VHD routing using a coreless substrate in accordance with some embodiments. FIG. 3 illustrates a system level diagram in accordance with some embodiments. FIG. 4 illustrates a method of substrate fabrication in accordance with some embodiments. FIG. 5 illustrates a method of coreless substrate fabrication in accordance with some embodiments. DETAILED DESCRIPTION The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims. Microelectronic substrates are generally composed of alternating layers of dielectric material and metal. The metal may be formed from copper, which is patterned to form conductive traces between components on the substrate. The dielectric material may be formed from inorganic materials, such as SiO2 or SiN, or organic materials. Some microelectronic substrates are formed using semiconductor materials, such as Si, while others may be formed from an organic monolithic core. One or more microelectronic die having integrated circuitry therein, may be physically and electrically attached to the substrate through various bonding techniques, such as ball bonding. The die may be attached to the substrate and connected such that signals are supplied between the die and traces in the substrate. In some embodiments, the signals from one die may be routed to another die through traces in the substrate. As above, bridge technologies may be used to provide interconnections to or between one or more die on a substrate. With the constant demand for increased proc