US-12628679-B2 - Semiconductor package

Abstract

A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a mold layer covering a side surface of the first semiconductor chip and a top surface of the first redistribution layer and having an upper surface coplanar with an upper surface of the first semiconductor chip, a metal layer on the first semiconductor chip and the mold layer to be in contact with upper surfaces of the mold layer and the first semiconductor chip, and a second redistribution layer on the metal layer.

Inventors

• Jongyoun KIM

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20230804

Priority Date

20221230

Claims (20)

1. 1 . A semiconductor package comprising: a first redistribution layer; a semiconductor chip on the first redistribution layer; a mold layer covering a side surface of the semiconductor chip and a top surface of the first redistribution layer and having an upper surface coplanar with an upper surface of the semiconductor chip; a metal layer in contact with and covering an upper surface of the semiconductor chip and a portion of an upper surface of the mold layer; and a second redistribution layer on the metal layer.
2. 2 . The semiconductor package of claim 1 , further comprising a plurality of mold vias passing through the mold layer and connected to the first redistribution layer and the metal layer, wherein the plurality of mold vias includes: a first mold via configured to receive a ground voltage; and a second mold via configured to receive a signal voltage.
3. 3 . The semiconductor package of claim 2 , wherein the metal layer includes: a first part connected to the first mold via; and a second part connected to the second mold via and spaced apart from the first part.
4. 4 . The semiconductor package of claim 3 , wherein the first part extends to cover upper surfaces of the semiconductor chip and the first mold via.
5. 5 . The semiconductor package of claim 3 , wherein the plurality of mold vias includes a plurality of first mold vias, and the first part extends to cover the plurality of first mold vias and the semiconductor chip.
6. 6 . The semiconductor package of claim 3 , wherein the second mold via is one of a plurality of second mold vias included in the plurality of mold vias, the second part of the metal layer is one of a plurality of second parts included in the metal layer, and the plurality of second parts correspond to the plurality of second mold vias in a one-to-one manner.
7. 7 . The semiconductor package of claim 1 , wherein a recess region is formed on an upper surface of the mold layer, and wherein the metal layer fills the recess region.
8. 8 . The semiconductor package of claim 7 , wherein the second redistribution layer includes a second redistribution pattern overlapping the recess region, and wherein a lower surface of the second redistribution pattern is flat.
9. 9 . The semiconductor package of claim 1 , wherein the metal layer includes a plurality of holes exposing the mold layer.
10. 10 . A semiconductor package comprising: a first redistribution layer; a semiconductor chip on the first redistribution layer; a plurality of mold vias spaced apart from the semiconductor chip on the first redistribution layer and having the same height as the semiconductor chip; a mold layer covering a side surface of the first semiconductor chip and a top surface of the first redistribution layer, having an upper surface coplanar with an upper surface of the semiconductor chip, and having a recess region formed on the upper surface thereof; a metal layer on the mold layer and filling the recess region; and a second redistribution layer on the metal layer.
11. 11 . The semiconductor package of claim 10 , wherein the plurality of mold vias include: a first mold via configured to receive a ground voltage; and a second mold via configured to receive a signal voltage, wherein the metal layer includes: a first part connected to the first mold via; and a second part connected to the second mold via and spaced apart from the first part.
12. 12 . The semiconductor package of claim 11 , wherein the first mold via is one of a plurality of first mold vias included in the plurality of mold vias, and the first part extends to cover the plurality of first mold vias and the semiconductor chip.
13. 13 . The semiconductor package of claim 11 , wherein the second mold via is one of a plurality of second mold vias included in the plurality of mold vias, the second part is one of a plurality of second parts included in the metal layer, and the plurality of second parts correspond to the plurality of second mold vias in a one-to-one manner.
14. 14 . The semiconductor package of claim 10 , wherein the second redistribution layer includes a second redistribution pattern overlapping the recess region, and wherein a lower surface of the second redistribution pattern is flat.
15. 15 . The semiconductor package of claim 10 , wherein the metal layer includes a plurality of holes exposing the mold layer.
16. 16 . A semiconductor package comprising: a first redistribution layer; a semiconductor chip on the first redistribution layer; a plurality of mold vias extending parallel to side surfaces of the semiconductor chip on the first redistribution layer and having the same height as the semiconductor chip, the plurality of mold vias including a first mold via configured to receive a ground and a second mold via configured to receive a signal voltage; a mold layer covering a side surface of the first semiconductor chip, a side surface of each of the plurality of mold vias, and a top surface of the first redistribution layer, having an upper surface coplanar with an upper surface of the semiconductor chip, and having a recess region formed on the upper surface thereof; a metal layer on the mold layer and filling the recess region, the metal layer including a first part connected to the first mold via, and a second part connected to the second mold via and spaced apart from the first part; and a second redistribution layer on the metal layer.
17. 17 . The semiconductor package of claim 16 , wherein the first part extends to cover the semiconductor chip and an upper surface of the first mold via.
18. 18 . The semiconductor package of claim 16 , wherein the first mold via is one of a plurality of first mold vias included in the plurality of mold vias, and the first part extends to cover the plurality of first mold vias and the semiconductor chip.
19. 19 . The semiconductor package of claim 16 , wherein the second mold via is one of a plurality of second mold vias included in the plurality of mold vias, the second part is one of a plurality of second parts included in the metal layer, and the plurality of second parts correspond to the plurality of second mold vias in a one-to-one manner.
20. 20 . The semiconductor package of claim 16 , wherein the metal layer includes a plurality of holes exposing the mold layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This U.S. non-provisional patent application claims priority under 35 U.S.C.§ 119 to Korean Patent Application No. 10-2022-0190349, filed on Dec. 30, 2022 in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION The present disclosure relates to a semiconductor package. A semiconductor package is provided to implement an integrated circuit chip to qualify for use in electronic products. Typically, a semiconductor package includes a semiconductor chip, which is mounted on a printed circuit board (PCB), and bonding wires or bumps, which electrically connect the semiconductor chip to the printed circuit board. With the development of electronics industry, various research has been conducted to improve reliability and durability of semiconductor packages. SUMMARY An object of the present disclosure is to provide a semiconductor package with improved reliability. A semiconductor package according to some embodiments of the present disclosure includes a first redistribution layer, a first semiconductor chip disposed on the first redistribution layer, a mold layer covering a side surface of the first semiconductor chip and a top surface of the first redistribution layer and having an upper surface coplanar with an upper surface of the first semiconductor chip, a metal layer disposed on the first semiconductor chip and the mold layer to be in contact with upper surfaces of the mold layer and the first semiconductor chip, and a second redistribution layer disposed on the metal layer. A semiconductor package according to some embodiments of the present disclosure includes a first redistribution layer, a first semiconductor chip disposed on the first redistribution layer, a plurality of mold vias spaced apart from the first semiconductor chip on the first redistribution layer and having the same height as the first semiconductor chip, a mold layer covering a side surface of the first semiconductor chip and a top surface of the first redistribution layer, having an upper surface coplanar with an upper surface of the first semiconductor chip, and having a recess region formed on the upper surface thereof, a metal layer disposed on the mold layer to fill the recess region, and a second redistribution layer disposed on the metal layer. A semiconductor package according to some embodiments of the present disclosure includes a first redistribution layer, a first semiconductor chip disposed on the first redistribution layer, a plurality of mold vias extending parallel to side surfaces of the first semiconductor chip on the first redistribution layer and having the same height as the first semiconductor chip, the plurality of mold vias including a first mold via configured such that a ground voltage is applied to the first mold via and a second mold via configured such that a signal voltage is applied to the second mold via, a mold layer covering a side surface of the first semiconductor chip, a side surface of each of the plurality of mold vias, and a top surface of the first redistribution layer, having an upper surface coplanar with an upper surface of the first semiconductor chip, and having a recessed region formed on the upper surface thereof, a metal layer disposed on the mold layer to fill the recess region, the metal layer including a first part connected to the first mold via, and a second part connected to the second mold via and spaced apart from the first part, and a second redistribution layer disposed on the metal layer. BRIEF DESCRIPTION OF THE DRAWINGS Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein. FIG. 1 is a plan view illustrating a semiconductor package according to some embodiments of the present disclosure. FIG. 2A is a cross-sectional view taken along line I-I′ of the semiconductor package of FIG. 1. FIG. 2B is an enlarged view illustrating a portion ‘P1’ of FIG. 2A. FIGS. 3A to 3I are cross-sectional views sequentially illustrating a process of manufacturing the semiconductor package of FIG. 2A. FIG. 4 is a plan view illustrating a semiconductor package according to some embodiments of the present disclosure. FIG. 5 is a cross-sectional view taken along line II-II′ of the semiconductor package of FIG. 4. FIG. 6 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure. FIG. 7 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure. FIG. 8 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure. DETAILED DESCRIPTION Hereinafter, to explain the present disclosure in more detail, embodiments according to the present dis