US-12628684-B2 - Semiconductor package

US12628684B2US 12628684 B2US12628684 B2US 12628684B2US-12628684-B2

Abstract

A semiconductor package includes a redistribution structure having a first surface, an opposite second surface, and a redistribution layer between the first surface and the second surface. A semiconductor chip is on the first surface of the redistribution structure and is electrically connected to the redistribution layer. An encapsulant is on at least a portion of the semiconductor chip. A passive element is on the second surface of the redistribution structure. The passive element includes a connection surface facing the second surface, a connection terminal on the connection surface, a non-connection surface opposite to the connection surface, and a side surface extending from the connection surface to the non-connection surface. A connection bump is adjacent the passive element on the second surface and is electrically connected to the redistribution layer. A sealing material is on at least a portion of the connection surface, the non-connection surface, and the side surface of the passive element.

Inventors

Jeonghyun LEE
Hwanpil PARK
JongBo Shim
Eunsu LEE
Jangwoo Lee

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20220615
Priority Date: 20211008

Claims (19)

1 . A semiconductor package comprising: a redistribution structure comprising a first surface, an opposite second surface, and a redistribution layer between the first surface and the second surface; a semiconductor chip on the first surface of the redistribution structure and electrically connected to the redistribution layer; an encapsulant on the semiconductor chip; a first passive element on the second surface of the redistribution structure, the first passive element comprising a connection surface facing the second surface of the redistribution structure, a connection terminal on the connection surface, a non-connection surface opposite to the connection surface, and a side surface extending from the connection surface to the non-connection surface; a second passive element on the second surface of the redistribution structure and spaced apart from the first passive element; a connection bump on the second surface of the redistribution structure and electrically connected to the redistribution layer, wherein the connection bump is adjacent to the first passive element; and a sealing material on each of the connection surface, the non-connection surface, and the side surface of the first passive element, wherein the sealing material selectively seals the first passive element without sealing the second passive element, wherein the first passive element comprises a silicon capacitor, and wherein the second passive element comprises a ceramic capacitor.
2 . The semiconductor package of claim 1 , wherein the sealing material is on an entirety of each of the connection surface and the non-connection surface of the first passive element.
3 . The semiconductor package of claim 1 , wherein a portion of the sealing material has a convex surface.
4 . The semiconductor package of claim 1 , wherein the sealing material has a maximum height that is lower than a maximum height of the connection bump in a direction perpendicular to the second surface.
5 . The semiconductor package of claim 1 , wherein a thickness of the sealing material on the non-connection surface of the first passive element is about 1 μm or greater.
6 . The semiconductor package of claim 1 , wherein the sealing material is on an entirety of the non-connection surface of the first passive element.
7 . The semiconductor package of claim 1 , wherein the sealing material comprises an insulating resin.
8 . The semiconductor package of claim 1 , wherein the first passive element further comprises a connection member between the second surface of the redistribution structure and the connection surface of the first passive element, wherein the connection member electrically connects the connection terminal to the redistribution layer.
9 . The semiconductor package of claim 8 , wherein the connection member comprises a portion electrically connected with the connection terminal and a solder portion electrically connecting the portion to the redistribution layer.
10 . The semiconductor package of claim 1 , wherein the sealing material comprises a first region on the connection surface of the first passive element and on the side surface of the first passive element, and a second region on the non-connection surface of the first passive element, wherein the first region and the second region are spaced apart from each other.
11 . The semiconductor package of claim 1 , wherein a portion of the sealing material on the non-connection surface has a flat surface.
12 . A semiconductor package comprising: a redistribution structure comprising a first surface, an opposite second surface, and a redistribution layer between the first surface and the second surface; a semiconductor chip on the first surface of the redistribution structure and electrically connected to the redistribution layer; a first passive element on the second surface of the redistribution structure, the first passive element comprising a first connection terminal and a first connection member electrically connecting the first connection terminal to the redistribution layer; a second passive element on the second surface of the redistribution structure, the second passive element comprising a second connection terminal and a second connection member electrically connecting the second connection terminal to the redistribution layer; and a sealing material on the first passive element, wherein the first passive element comprises a silicon (Si) capacitor and the second passive element comprises a ceramic capacitor.
13 . The semiconductor package of claim 12 , wherein the sealing material does not contact the second passive element.
14 . The semiconductor package of claim 12 , wherein the first connection member comprises a first portion electrically connected with the first connection terminal, and a first solder portion electrically connecting the first portion to the redistribution layer, and the second connection member comprises a second solder portion electrically connecting the second connection terminal to the redistribution layer.
15 . The semiconductor package of claim 12 , wherein the redistribution layer comprises a first pad electrically connected with the first connection member, and a second pad electrically connected with the second connection member, and the first pad has a first width in a direction that is parallel to the second surface, the second pad has a second width in the direction, and wherein the first width is less than the second width.
16 . A semiconductor package comprising: a redistribution structure comprising a plurality of insulating layers and a plurality of redistribution layers between the plurality of insulating layers, wherein an uppermost one of the plurality of insulating layers forms a first surface of the redistribution structure, and wherein a lowermost one of the plurality of insulating layers forms an opposite second surface of the redistribution structure; a semiconductor chip on the first surface of the redistribution structure and electrically connected to the plurality of redistribution layers; a passive element on the second surface of the redistribution structure, the passive element comprising a connection surface facing the second surface of the redistribution structure, an opposite non-connection surface, and a connection terminal on the connection surface; and a sealing material on the non-connection surface of the passive element, wherein the lowermost one of the plurality of insulating layers comprises a trench therein at the second surface of the redistribution structure, wherein the trench has a bottom surface recessed away from the connection surface, and wherein the sealing material extends from the non-connection surface of the passive element to the bottom surface of the trench.
17 . The semiconductor package of claim 16 , further comprising: a connection bump on the second surface of the redistribution structure and electrically connected to the plurality of redistribution layers, wherein the connection bump and the passive element are in adjacent, spaced-apart relationship.
18 . The semiconductor package of claim 16 , wherein the trench is configured such that at least a portion of an insulating layer on the lowermost one of the plurality of insulating layers is uncovered.
19 . The semiconductor package of claim 18 , wherein the sealing material is on the at least a portion of the insulating layer that is uncovered.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims benefit of priority to Korean Patent Application No. 10-2021-0134153 filed on Oct. 8, 2021 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND The present inventive concept relates to a semiconductor package. Semiconductor packages in which a high-performance semiconductor chip is embedded may have problems, such as malfunctions and system performance degradation due to voltage noise occurring in a high-frequency band. Therefore, there is a need for improved packaging technology. SUMMARY An aspect of the present inventive concept is to provide a semiconductor package having improved power integrity (PI) characteristics. According to an aspect of the present inventive concept, a semiconductor package includes a redistribution structure having a first surface, an opposite second surface, and a redistribution layer between the first surface and the second surface; a semiconductor chip on the first surface of the redistribution structure and electrically connected to the redistribution layer; an encapsulant on the semiconductor chip on the first surface of the redistribution structure; a passive element on the second surface of the redistribution structure, the passive element having a connection surface facing the second surface of the redistribution structure, a connection terminal on the connection surface, a non-connection surface opposite to the connection surface, and a side surface extending from the connection surface to the non-connection surface; a connection bump on the second surface of the redistribution structure and electrically connected to the redistribution layer, wherein the connection bump is adjacent to the passive element; and a sealing material on each of the connection surface, the non-connection surface, and the side surface of the passive element. According to an aspect of the present inventive concept, a semiconductor package includes a redistribution structure having a first surface, an opposite second surface, and a redistribution layer between the first surface and the second surface; a semiconductor chip on the first surface of the redistribution structure and electrically connected to the redistribution layer; a first passive element on the second surface of the redistribution structure, the first passive element including a first connection terminal and a first connection member electrically connecting the first connection terminal to the redistribution layer; a second passive element on the second surface of the redistribution structure and electrically connecting the second connection terminal to the redistribution layer; and a sealing material on the first passive element, wherein the first passive element includes a silicon (Si) capacitor and the second passive element includes a ceramic capacitor. According to an aspect of the present inventive concept, a semiconductor package includes: a redistribution structure including a plurality of insulating layers and a plurality of redistribution layers between the plurality of insulating layers, wherein an uppermost one of the plurality of insulating layers forms a first surface of the redistribution structure, and wherein a lowermost one of the plurality of insulating layers forms an opposite second surface of the redistribution structure; a semiconductor chip on the first surface of the redistribution structure and electrically connected to the redistribution layer; a passive element on the second surface of the redistribution structure, the passive element having a connection surface facing the second surface, an opposite non-connection surface, and a connection terminal on the connection surface; and a sealing material on the non-connection surface of the passive element, wherein the lowermost one of the plurality of insulating layers has a trench therein at the second surface of the redistribution structure, and wherein the sealing material is in the trench. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects, features, and advantages of the present inventive concept will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: FIG. 1A is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the present inventive concept, FIG. 1B is a partially enlarged view illustrating region ‘A’ of FIG. 1A, and FIG. 1C is a plan view illustrating a portion of a lower surface of a semiconductor package including a portion illustrated in FIG. 1B; FIG. 2 is a partially enlarged view illustrating a modified example of a semiconductor package according to an example embodiment of the present inventive concept; FIG. 3 is a partially enlarged view illustrating a modified example of a semiconductor package according to an example embodiment of the present inventive concept; FIG. 4A