US-12628686-B2 - Techniques to enable a flip chip underfill exclusion zone

Abstract

Example techniques to enable a flip chip underfill exclusion zone include use of bump barriers, films or etched substrate cavities to prevent underfill from reaching the flip chip underfill exclusion zone.

Inventors

• Ronald Spreitzer
• Jason Garcia
• Ankur Agrawal
• Eleanor Patricia Paras Rabadam
• Guiyun Bai

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260512

Application Date

20211223

Claims (20)

1. 1 . A microelectronic assembly comprising: a die substrate to include a component, the component to have an area on a flip chip side of the die substrate identified as an underfill exclusion zone; a plurality of die bumps on the flip chip side to enable the die substrate to electrically couple to a carrier substrate that is configured to route signals received through the plurality of die bumps; and a film barrier deposited on the die substrate to cover at least a perimeter around the underfill exclusion zone such that an underfill material, when used to improve a solder joint reliability of the die bumps, is prevented from reaching to the underfill exclusion zone, wherein the film barrier is deposited on the die substrate as a lithographic film deposited in one or more layers to reach a thickness that substantially matches a height of the plurality of die bumps, and wherein the lithographic film is to be deposited over a surface that also covers the underfill exclusion zone, the lithographic film to be deposited over the surface such that an additional width of lithographic film deposited over the surface is sufficient to prevent the underfill material from flowing underneath the additional width of lithographic film and reaching the underfill exclusion zone.
2. 2 . The microelectronic assembly of claim 1 , the component comprises a silicon photonics component or a micro-electromechanical system (MEMS) component.
3. 3 . The microelectronic assembly of claim 2 , the silicon photonics component comprises a semiconductor optical amplifier.
4. 4 . The microelectronic assembly of claim 3 , wherein the plurality of die bumps on the flip chip side couple the semiconductor optical amplifier with a carrier substrate to enable the semiconductor optical amplifier to electrically couple with a trans-impedance amplifier (TIA).
5. 5 . The microelectronic assembly of claim 2 , wherein the microelectronic assembly is included in a light detection and ranging (LiDAR) silicon photonics system on a chip or a MEMS chip.
6. 6 . The microelectronic assembly of claim 1 , the underfill material comprising an epoxy underfill material.
7. 7 . A method for assembling at least a portion of a microelectronic assembly, comprising: identifying an area on a flip chip side of a die substrate as an underfill exclusion zone for a component included in the die substrate; and depositing a film barrier on the die substrate to cover at least a perimeter around the underfill exclusion zone such that an underfill material, when used to improve a solder joint reliability of die bumps, is prevented from reaching the underfill exclusion zone, wherein the film barrier is deposited on the die substrate as a lithographic film in one or more layers to reach a thickness that substantially matches a height of a plurality of die bumps on the flip chip side of the die substrate that are arranged to enable the die substrate to electrically couple to a carrier substrate, and wherein the lithographic film is deposited over a surface that also covers the underfill exclusion zone, the lithographic film to be deposited over the surface such that an additional width of lithographic film deposited over the surface is sufficient to prevent the underfill material from flowing underneath the additional width of lithographic film and reaching the underfill exclusion zone.
8. 8 . The method of claim 7 , the component comprises a silicon photonics component or a micro-electromechanical system (MEMS) component.
9. 9 . The method of claim 8 , the silicon photonics component comprises a semiconductor optical amplifier.
10. 10 . The method of claim 7 , the underfill material comprising an epoxy underfill material.
11. 11 . A microelectronic assembly comprising: a die substrate to include a component, the component to have an area on a flip chip side of the die substrate identified as an underfill exclusion zone; a plurality of die bumps on the flip chip side to enable the die substrate to electrically couple to a carrier substrate that is configured to route signals received through the plurality of die bumps; and a bump barrier to include a plurality of bumps arranged around the underfill exclusion zone such that an underfill material, when used to improve a solder joint reliability of the plurality of die bumps, is prevented from reaching the underfill exclusion zone, wherein the plurality of bumps are arranged around the underfill exclusion zone as a perimeter wall of a single bump thickness, each bump in the perimeter wall arranged to not contact bumps on either side, wherein a distance between each bump in the perimeter wall is close enough to prevent the underfill material from flowing far enough to reach the underfill exclusion zone.
12. 12 . The microelectronic assembly of claim 11 , the component comprises a silicon photonics component or a micro-electromechanical system (MEMS) component.
13. 13 . The microelectronic assembly of claim 12 , the silicon photonics component comprises a semiconductor optical amplifier.
14. 14 . The microelectronic assembly of claim 11 , the underfill material comprising an epoxy underfill material.
15. 15 . A microelectronic assembly comprising: a die substrate to include a component, the component to have an area on a flip chip side of the die substrate identified as an underfill exclusion zone; a plurality of die bumps on the flip chip side to enable the die substrate to electrically couple to a carrier substrate that is configured to route signals received through the plurality of die bumps; and a low modulus film deposited on the die substrate to cover the underfill exclusion zone such that an underfill material, when used to improve a solder joint reliability of the plurality of die bumps, is prevented from flowing to the underfill exclusion zone.
16. 16 . The microelectronic assembly of claim 15 , wherein the low modulus film comprises a material that is capable of being cured at a same time as the underfill material when applied to the carrier substrate.
17. 17 . The microelectronic assembly of claim 15 , wherein the low modulus film comprises a material that is capable of absorbing at least some heat generated by the component while the component is operating.
18. 18 . The microelectronic assembly of claim 15 , the component comprises a silicon photonics component or a micro-electromechanical system (MEMS) component.
19. 19 . The microelectronic assembly of claim 15 , the underfill material comprising an epoxy underfill material.
20. 20 . A microelectronic assembly comprising: a die substrate to include a component, the component to have an area on a flip chip side of the die substrate identified as an underfill exclusion zone; a plurality of die bumps on the flip chip side to enable the die substrate to electrically couple to a carrier substrate that is configured to route signals received through the plurality of die bumps; and a substrate cavity on the carrier substrate located below the underfill exclusion zone such that an underfill material, when used to improve a solder joint reliability of the plurality of die bumps, is prevented from contacting the underfill exclusion zone due to the underfill material flowing into the substrate cavity.

Description

TECHNICAL FIELD Examples described herein are generally related to techniques to enable a flip chip underfill exclusion zone for silicon-based packaging. BACKGROUND System on a chip (SoC) that includes one or more silicon photonics components used in such applications as light detection and ranging (LiDAR) or silicon-based micro-electromechanical systems (MEMS) may have relative larger die size to accommodate these types of devices as compared to other types of SoCs (e.g., central processing unit SoCs). A larger die size may increase a need to utilize flip chip technologies to enable an SoC to have more components and yet attempt to reduce die size increases to accommodate more components. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a bottom view of a first example microelectronic assembly. FIG. 2 illustrates a cross-sectional and expanded cross-sectional view of a second example microelectronic assembly. FIGS. 3A-C illustrate bottom and cross-sectional views of a third example microelectronic assembly. FIG. 4 illustrates an example first process flow. FIGS. 5A-C illustrate bottom and cross-sectional views of a fourth example microelectronic assembly. FIG. 6 illustrates an example second process flow. FIGS. 7A-B illustrate a bottom view of a first example substrate die of a microelectronic assembly with an expanded view of a first example bump barrier. FIG. 8 illustrates an example third process flow. FIGS. 9A-B illustrate a bottom view of a second example substrate die of a microelectronic assembly with an expanded view of a second example bump barrier. FIG. 10 illustrates an example fourth process flow. FIG. 11 illustrates a bottom and a cross-sectional view of a fifth example microelectronic assembly. FIG. 12 illustrates an example fifth process flow. FIG. 13 illustrates a bottom and a cross-sectional view of a sixth example microelectronic assembly. FIG. 14 illustrates an example sixth process flow. DETAILED DESCRIPTION As contemplated by this disclosure, a large die size associated with an SoC that includes one or more silicon photonics components or MEMs increases a need to use a flip chip side on the SoC to enable additional components to be added while minimizing increases in die size. A current generation of LiDAR sensor architectures have limitations with respect to subsequent generation product requirements. Enabling flip chip packaging for these subsequent generation products will help to mitigate various issues related to SoCs having large die sizes. For example, large/un-optimized die size, high optical loss (correlated with die size), low die yield/high die cost (correlated with die size), long manufacturing flow/process duration, higher manufacturing costs (correlated with flow complexity) and signal integrity degradation. Various attempts to enable flip chip packaging include a use of substrate based dams/trenches to restrict underfill flow outside of a flip chip area, die based plated bar structures to also restrict underfill, or a complete underfilling between a die and a carrier substrate. The use of dams/trenches has limitations such as barrier structures are typically wide and require corresponding large exclusion zones on the die that may result in unacceptably increasing die size and die cost. The use of plated bar structures may also have limitations such as geometry/surface area/electrical resistance of a given bar barrier structure on a die is likely to be different than solder balls or bumps of the die that are formed during a same process step. This difference results in different growth rates and heights between bumps on the die and the given bar barrier structure. The different growth rates and heights can result in the given barrier structure becoming a standoff which prevents other bumps on the die from being able to electrically connect to a carrier substrate. In some cases, plating rates for bumps vs. bar structures may be significant enough to require bumps and bar structures to be formed in 2 separate electro plating processes that would result in additional processing steps/costs. Complete underfilling also has significant limitations to enable flip chip packaging. Silicon photonics have a performance and reliability risk when localized stresses are present in sensitive optical active/pool regions on flip chip side of an SoC die. Complete underfill coverage results in an epoxy included in the underfill material to bond to the SoC die in the sensitive optical active/pool regions. A resulting stress transfer to the sensitive optical active/pool regions during temperature cycling due to this epoxy bonding may unacceptably impact a silicon photonics component's performance and reliability. It is with respect to these challenges that the examples described herein are needed. FIG. 1 illustrates an example bottom view of a microelectronic assembly 100. In some examples, as shown in FIG. 1, the bottom view of microelectronic assembly 100 includes an input 101, an outpu