US-12628687-B2 - Semiconductor device and method of manufacturing the same

US12628687B2US 12628687 B2US12628687 B2US 12628687B2US-12628687-B2

Abstract

A semiconductor device includes a first substrate, an electronic component, and a lid. The first substrate includes a first substrate top side, a first substrate bottom side opposite to the first substrate top side, a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side, and a connector structure. The electronic component is coupled to the first substrate top side and coupled to the connector structure. The lid includes a wall part including a ring part coupled to the first substrate top side, a first part of an overhang part coupled to the first substrate lateral side, and a second part of the overhang part extending from the first part of the overhang part away from the first substrate lateral side.

Inventors

KUAN-YU HUANG
Sung-Hui Huang
Shang-Yun Hou
Chien-Yuan Huang

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260512
Application Date: 20231122

Claims (20)

1 . A semiconductor device comprising: a first substrate comprising: a first substrate top side; a first substrate bottom side opposite to the first substrate top side; a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side; and a connector structure; a second substrate comprising a second substrate top side, wherein the first substrate is coupled to the second substrate top side: an electronic component coupled to the first substrate top side and coupled to the connector structure; and a lid comprising: a wall part comprising: a ring part coupled to the first substrate top side; a first part of an overhang part coupled to the first substrate lateral side; and a second part of the overhang part extending from the first part of the overhang part away from the first substrate lateral side, wherein the ring part of the wall part is coupled to the first substrate top side with a first adhesive; the first part of the overhang part is coupled to the first substrate lateral side with a second adhesive; and the second part of the overhang part is coupled to the second substrate top side with a third adhesive, wherein at least one of the first adhesive and the second adhesive is in physical contact with the first substrate.
2 . The semiconductor device of claim 1 , wherein the electronic component comprises a package, and the semiconductor structure further comprises an underfill material between the first substrate top side of the first substrate and the electronic component, and surrounding the connector structure and bottom sidewalls of the electronic component.
3 . The semiconductor device of claim 1 , wherein the second part of the overhang part has a bottom surface, and an area of the bottom surface is less than an area of a bottom surface of the ring part.
4 . The semiconductor device of claim 1 , wherein the second part of the overhang part is positioned below the first substrate bottom side.
5 . The semiconductor device of claim 4 , wherein the lid further comprises: a cap part coupled to the wall part and extending to overlap the electronic component.
6 . The semiconductor device of claim 5 , wherein the cap part has an opening exposing a top surface of the electronic component.
7 . The semiconductor device of claim 5 , further comprising: a thermal interface material interposed between the electronic component and the cap part.
8 . The semiconductor device of claim 7 , wherein the thermal interface material comprises thermal conductive filler material.
9 . The semiconductor device of claim 1 , further comprising: a second substrate comprising: a second substrate top side; a second substrate bottom side opposite to the second substrate top side; and a second substrate lateral side interposed between the second substrate top side and the second substrate bottom side, wherein: the first substrate is coupled to the second substrate top side; and the second part of the overhang part is coupled to the second substrate top side.
10 . The semiconductor device of claim 9 , wherein the lid further comprises a protrusion part extending from outer sidewalls of the second part of the overhang part toward edges of the second substrate, and the protrusion part is coupled to the second substrate top side.
11 . The semiconductor device of claim 1 , wherein the first adhesive and the second adhesive are physically separated from each other, and one of the first adhesive and the second adhesive has an inclined sidewall.
12 . A semiconductor device comprising: a first substrate comprising: a first substrate top side; a first substrate bottom side opposite to the first substrate top side; a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side along a first direction; and a connector structure; an electronic component coupled to the first substrate top side and coupled to the connector structure; and a lid comprising: a wall part comprising: a ring part coupled to the first substrate top side and having a first width along a second direction substantially perpendicular to the first direction, wherein the ring part has a stepped sidewall facing the electronic component; a first part of an overhang part coupled to the first substrate lateral side and having a second width different from the first width along the second direction; and a second part of the overhang part coupled to the first substrate lateral side through the first part of the overhang part.
13 . The semiconductor device of claim 12 , wherein the second part of the overhang part has a third width substantially the same as or larger than the second width.
14 . The semiconductor device of claim 12 , further comprising a second substrate, wherein the lid is adhered to the second substrate through the second part of the overhang part.
15 . The semiconductor device of claim 12 , further comprising a cap part coupled to the wall part and protruded from an inner sidewall of the ring part.
16 . The semiconductor device of claim 12 , wherein a projection of the ring part onto the first substrate is separated from a projection of the electronic component onto the first substrate.
17 . The semiconductor device of claim 12 , wherein the ring part has a bottom surface coupled to the first substrate top side and an exposed top surface, the stepped sidewall is disposed between the exposed top surface and the bottom surface, and the first part of the overhang part is in physical contact with the first substrate lateral side.
18 . The semiconductor device of claim 12 , wherein the first part of the overhang part is in physical contact with an entirety of the first substrate lateral side.
19 . A semiconductor device comprising: a first substrate comprising: a first substrate top side; a first substrate bottom side opposite to the first substrate top side; a first substrate lateral side interposed between the first substrate top side and the first substrate bottom side; and a connector structure; an electronic component coupled to the first substrate top side and coupled to the connector structure; and a lid comprising: a wall part comprising: a ring part coupled to the first substrate top side; a first part of an overhang part coupled to the first substrate lateral side; and a second part of the overhang part extending from the first part of the overhang part away from the first substrate lateral side, wherein the second part of the overhang part is positioned below the first substrate bottom side; and a cap part coupled to the wall part and extending to overlap the electronic component, wherein the cap part has an opening exposing a top surface of the electronic component.
20 . The semiconductor device of claim 19 , wherein: the ring part of the wall part is coupled to the first substrate top side with a first adhesive; and the first part of the overhang part is coupled to the first substrate lateral side with a second adhesive.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application of and claims the priority benefit of a prior application Ser. No. 17/874,326, filed on Jul. 27, 2022. The prior application Ser. No. 17/874,326 is a divisional application of and claims the priority benefit of a prior application Ser. No. 16/920,408, filed on Jul. 2, 2020. The prior application Ser. No. 16/920,408 claims the priority benefit of U.S. provisional application Ser. No. 62/953,469, filed on Dec. 24, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. BACKGROUND The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged. An example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. Another example is a Chip-On-Wafer-On-Substrate (CoWoS) structure, where a semiconductor chip is attached to a wafer (e.g., an interposer) to form a Chip-On-Wafer (CoW) structure. The CoW structure is then attached to a substrate (e.g., a printed circuit board) to form a CoWoS structure. These and other advanced packaging technologies enable production of semiconductor devices with enhanced functionalities and small footprints. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A through 5A illustrate cross-sectional views of intermediate stages of manufacturing a semiconductor structure in accordance with various embodiments. FIGS. 1B through 5B illustrate top views of intermediate stages of manufacturing the semiconductor structure of FIGS. 1A through 5A. FIG. 6 illustrates a perspective view of the semiconductor structure of the FIG. 5A. FIGS. 7A, 7B, 8A, 9A and 10A illustrate cross-sectional views of semiconductor structures in accordance with various embodiments. FIGS. 8B through 10B illustrate top views of the semiconductor structure of FIGS. 8A through 10A. FIG. 11 is a flow diagram illustrating a method of fabricating semiconductor structures in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verificati