US-12628692-B2 - Semiconductor package, semiconductor bonding structure, and method of fabricating the same

US12628692B2US 12628692 B2US12628692 B2US 12628692B2US-12628692-B2

Abstract

The present disclosure relates to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. The semiconductor package includes a first chip, a second chip and a conductive structure, wherein the conductive structure is disposed at a side of the second chip and over a second upper surface of the first interconnection structure to electrically connect to the first interconnection structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnection structures, a plurality of chips and a plurality of conductive structures, wherein the conductive structures are respectively disposed at a side of each of the chips and over a second upper surface of each first interconnection structure, to electrically connect to each first interconnection.

Inventors

Kai-Kuang Ho
YU-JIE LIN
Yi-Feng Hsu

Assignees

UNITED MICROELECTRONICS CORP.

Dates

Publication Date: 20260512
Application Date: 20221117
Priority Date: 20221011

Claims (4)

1 . A semiconductor package, comprising: a first chip, comprising: a first substrate; and a first interconnection structure disposed on the first substrate, wherein an upper surface of the first interconnection structure comprises a first upper surface and a second upper surface; a second chip stacked on the first chip, the second chip comprising: a second substrate; and a second interconnection structure disposed on the second substrate, wherein the second interconnection structure directly and electrically connects to the first upper surface of the first interconnection structure; and a conductive structure, disposed at one side of the second chip and on the second upper surface of the first interconnection structure, the conductive structure electrically connected to the first interconnection structure, wherein the first upper surface of the first interconnection structure directly in contact and electrically connecting to the second interconnection structure is separated from the second upper surface of the first interconnection structure directly in contact and electrically connecting to the conductive structure.
2 . The semiconductor package according to claim 1 , wherein the conductive structure comprises at least one solder pillar, and a portion of the solder pillar is protruded from a surface of the second chip.
3 . The semiconductor package according to claim 1 , wherein the first interconnection structure of the first chip further comprises: a bonding pad embedded in the first interconnection structure, and the bonding pad electrically connected to the conductive structure.
4 . The semiconductor package according to claim 1 , further comprising: a molding layer, covered on the second chip and the first interconnection structure, wherein the conductive structure is partially disposed in the molding layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present disclosure relates to a semiconductor technology, and more particularly, to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. 2. Description of the Prior Art In advanced semiconductor industry, integration density of various electronic components has been continuously improved by reducing minimum feature size, which allows more electronic components to be integrated into given areas. These smaller electronic components also require smaller packages that utilize less area than the conventional packages. Three dimensional integrated circuits (3DICs) refer to a three-dimensional stack of chips formed by using wafer-level bonding and through-silicon-via (TSV) technologies. In comparison with conventional two-dimensional chips, the 3DICs may have the advantages of using the space more effectively, shorter signal transmission distances between chips, and lower interconnecting resistances. The 3DICs have gradually become the mainstream technology of power converters, low noise amplifiers, radio frequency (RF) or millimeter wave (MMW) components. Furthermore, the 3DICs may also be achieved by placing chips over chips of a wafer-level, or forming a bonding interface between the chips by a hybrid bonding process. The hybrid bonding (also known as “metal/dielectric hybrid bonding”) may be a direct bonding technology without using intermediate layers like solder bond or adhesives, which obtains metal-to-metal bonding and dielectric-to-dielectric bonding simultaneously, so as to overcome the fabrication limits of the micro bump technology. However, the current 3DICs still have problems need to be further improved to meet the semiconductor industrial requirements. SUMMARY OF THE INVENTION In light of the above, the present disclosure is directed to provide a semiconductor package, a semiconductor bonding structure, and a method of fabricating the same, in which the semiconductor package is fabricated by copper-to-copper direct bonding in a chip-to-wafer bonding manner, and the chip and a conductive structure are respectively bonded to two different upper surfaces of an interconnection structure of the wafer. Accordingly, the copper-to-copper direct bonding is not only capable to replace the conventional through-silicon-via (TSV) structure, simplifying the fabricating complexity and cost of the TSV, but also improves the structural defects possibly derived from the TSV structure. Therefore, the present disclosure is allowable to form the semiconductor package with more reliable structure under a simplified fabricating process, with the conductive structure being disposed at a location higher than the chip, so as to facilitate the arrangements of input/output terminals in the subsequent fabricating processes. According to an embodiment of the present disclosure, a semiconductor package is provided and includes a first chip, a second chip, and a conductive structure. The first chip includes a first substrate and a first interconnection structure disposed on the first substrate, wherein an upper surface of the first interconnection structure includes a first upper surface and a second upper surface. The second chip is stacked on the first chip, and the second chip includes a second substrate and a second interconnection structure disposed on the second substrate, wherein the second interconnection structure directly and electrically connects to the first upper surface of the first interconnection structure. The conductive structure is disposed at one side of the second chip, on the second upper surface of the first interconnection structure, and the conductive structure electrically connected to the first interconnection structure. According to an embodiment of the present disclosure, a semiconductor bonding structure is provided and includes a primary substrate, a plurality of first interconnection structures, a plurality of chips, and a plurality of conductive structures. The plurality of first interconnection structures is disposed on the primary substrate, wherein an upper surface of each of the first interconnection structures includes a first upper surface and a second upper surface. The plurality of chips is disposed on the first interconnection structures and electrically connected to the first interconnection structures respectively, and each of the chips includes a substrate and a second interconnection structure disposed on the substrate, wherein the second interconnection structure directly and electrically connects to the first upper surface of each of the first interconnection structures. The plurality of conductive structures is disposed at one side of each of the chips, on the second upper surface of each of the first interconnection structures, and the conductive structures electrically connects to the first interconnection structures respectively. According to an embodiment of the present disclos