US-12628693-B2 - Semiconductor package and method of manufacturing semiconductor package

Abstract

A method for forming a package includes: molding a semiconductor chip and a light-emitting element; forming a redistribution layer (RDL) which electrically connects the semiconductor chip to the light-emitting element; and arranging a light-receiving element on the redistribution layer to be electrically connected thereto. The light-receiving element is arranged such that at least a portion thereof is located directly above the semiconductor chip.

Inventors

• Dong Woo Park
• Seong Wook Choi

Assignees

• LIPAC CO., LTD.

Dates

Publication Date

20260512

Application Date

20210615

Priority Date

20200615

Claims (20)

1. 1 . A method of manufacturing a package, comprising operations of: molding a semiconductor chip and a light-emitting element within a mold; forming a redistribution layer (RDL) configured to electrically connect the semiconductor chip and the light-emitting element; and arranging a light-receiving element on the redistribution layer to electrically connect the light-receiving element and the redistribution layer, wherein the light-receiving element is arranged outside the mold such that at least a portion of the light-receiving element is located directly above the semiconductor chip, wherein the method further comprises: an operation of attaching a conductive metal pattern to a back surface of the light- emitting element before the molding, wherein the molding is performed by molding the light-emitting element and the conductive metal pattern attached to the light-emitting element together.
2. 2 . The method of claim 1 , further comprising an operation of attaching a conductive metal pattern to a back surface of the semiconductor chip before the molding, wherein the molding is performed by molding the semiconductor chip and the conductive metal pattern attached to the semiconductor chip together.
3. 3 . The method of claim 2 , further comprising an operation of exposing the conductive metal pattern attached to the light-emitting element and the conductive metal pattern attached to the semiconductor chip.
4. 4 . The method of claim 1 , wherein the molding is performed by further molding a conductive rod having an external connection terminal formed thereon together with a conductive metal pattern attached to the semiconductor chip and a conductive metal pattern attached to the light-emitting element.
5. 5 . The method of claim 4 , further comprising an operation of exposing the external connection terminal.
6. 6 . The method of claim 4 , wherein the external connection terminal is one of a solder ball, a conductive bump, and a pad.
7. 7 . The method of claim 1 , wherein the molding includes an operation of further molding a sacrificial member having a lower hardness than the mold, and the method of manufacturing a package further comprises operations of: perforating the sacrificial member to form a through hole; and forming a conductive material in the through hole.
8. 8 . The method of claim 1 , wherein the operation of forming the redistribution layer includes operations of: forming a wire pattern configured to electrically connect the semiconductor chip and the light-emitting element; and forming an insulating layer configured to passivate the wire pattern, the semiconductor chip, and the light-emitting element.
9. 9 . The method of claim 8 , wherein: the operation of forming the redistribution layer further includes an operation of forming a pad electrically connected to the wire pattern; and the operation of forming the pad includes operations of removing the insulating layer to expose the wire pattern, performing plating so that the pad electrically connected to the exposed wire pattern is formed, and coating the pad.
10. 10 . The method of claim 1 , further comprising an operation of forming one of an optical member and a diffuser on an optical path of light provided by the light-emitting element.
11. 11 . The method of claim 10 , further comprising an operation of removing at least a portion of the redistribution layer located on the optical path before forming one of the optical member and the diffuser.
12. 12 . A package comprising: a light-emitting element; a light-receiving element; a semiconductor chip on which a semiconductor circuit is formed; a mold configured to encapsulate the semiconductor chip and the light-emitting element; a redistribution layer configured to electrically connect the light-emitting element, the light-receiving element, and the semiconductor chip; a through via electrically connected to the redistribution layer and passing through the mold; and an external connection terminal electrically connected to the through via, wherein at least a portion of the light-receiving element is located directly above the semiconductor chip, wherein the light-emitting element has a conductive metal pattern attached to a back surface of the light-emitting element, wherein the mold encapsulates the light-emitting element and the conductive metal pattern attached to the light-emitting element together, wherein the through via includes a conductive rod that electrically connects the redistribution layer to the external connection terminal, and a shell that is molded together with the conductive rod and encapsulates the conductive rod, and wherein the light-receiving element is disposed outside the mold.
13. 13 . The package of claim 12 , wherein: the light-emitting element is one of a vertical cavity surface emitting laser (VCSEL) and a light-emitting diode (LED); and the light-receiving element is one of a photodiode (PD), a CMOS image sensor (CIS), and a single photon avalanche diode (SPAD).
14. 14 . The package of claim 12 , wherein the semiconductor circuit includes one or more of a light-emitting element driving circuit, a light-receiving element driving circuit, and a time of flight (TOF) arithmetic circuit.
15. 15 . The package of claim 12 , wherein the redistribution layer includes an insulating layer configured to passivate the semiconductor package, and a wire pattern configured to electrically connect the light-emitting element, the light-receiving element, and the semiconductor chip.
16. 16 . The package of claim 12 , wherein an insulating layer is formed as one of a polyimide layer, a polymer layer, and an oxide layer.
17. 17 . The package of claim 12 , wherein the external connection terminal is one of a solder ball, a conductive bump, and a pad.
18. 18 . The package of claim 12 , further comprising one of an optical member and a diffusion member formed on an optical path of the light-emitting element.
19. 19 . The package of claim 18 , wherein: at least a portion of an insulating layer is removed on the optical path; and one of a light-emitting element lens unit and a diffusion unit is formed on the optical path.
20. 20 . The package of claim 18 , further comprising: one of the light-emitting element lens unit and a diffusion unit; and a holder in which a light-receiving element lens unit formed on an optical path of the light-receiving element is located.

Description

CROSS-REFERENCE TO PRIOR APPLICATIONS This application is a National Stage Patent Application of PCT International Patent Application No. PCT/KR2021/007437 (filed on Jun. 15, 2021) under 35 U.S.C. § 371, which claims priority to Korean Patent Application No. 10-2020-0072530 (filed on Jun. 15, 2020), which are all hereby incorporated by reference in their entirety. BACKGROUND The present technology relates to a semiconductor package and a method of manufacturing the semiconductor package. Technology of reconstructing a distance from a subject and a three-dimensional image of the subject by emitting a laser and using a time difference of light reflected from the subject is being applied in various fields such as mobile devices, automobiles, medical care, and the like. In order to implement this technology, a light-emitting element, a light-receiving element, and a chip which drives these elements and performs signal processing are required. In order to realize this in a mobile platform, lightening, thinning, and miniaturizing an optical element package are essentially required. SUMMARY Most currently used packages have large areas and complicated process operations. The embodiment is directed to solving the above-described difficulties of the related art. That is, providing a method capable of forming a semiconductor package including an optical element with a small area and a thin thickness is one of the problems to be solved by the present technology. Further, optical members such as a lens, a diffuser, and the like are mainly used to manufacture a module, and additional component and assembly costs may be reduced, and the package itself may be manufactured with a smaller size by manufacturing the optical members directly on a semiconductor package at a wafer level. A method of manufacturing a package according to the embodiment includes operations of: molding a semiconductor chip and a light-emitting element; forming a redistribution layer (RDL) configured to electrically connect the semiconductor chip and the light-emitting element; and arranging a light-receiving element on the redistribution layer to electrically connect the light-receiving element and the redistribution layer, wherein the light-receiving element is arranged so that at least a portion of the light-receiving element is located directly above the semiconductor chip. A package according to the embodiment includes: a light-emitting element; a light-receiving element; a semiconductor chip on which a semiconductor circuit is formed; a mold configured to encapsulate the semiconductor chip and the light-emitting element; a redistribution layer configured to electrically connect the light-emitting element, the light-receiving element, and the semiconductor chip; a through via electrically connected to the redistribution layer and passing through the mold; and an external connection terminal electrically connected to the through via, wherein at least a portion of the light-receiving element is located directly above the semiconductor chip. A package according to the embodiment includes: a light-emitting element; a semiconductor chip on which a semiconductor circuit is formed; a mold configured to encapsulate the semiconductor chip and the light-emitting element; a redistribution layer configured to electrically connect the light-emitting element and the semiconductor chip; a through via electrically connected to the redistribution layer and passing through the mold; and an external connection terminal electrically connected to the through via, wherein a conductive metal pattern is located on a bottom surface of the light-emitting element. According to the embodiment, there is an advantage that an optical element package occupying a small area through a simple process is provided. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart illustrating an outline of a method of manufacturing a semiconductor package according to the embodiment. FIG. 2 is a view illustrating a result of performing an operation of molding a light-emitting element and a semiconductor chip. FIG. 3, (a) is a view illustrating a light-emitting surface of the light-emitting element, and FIG. 3, (b) is a view schematically illustrating a cross-section of the light-emitting element. FIG. 3, (c) is a view schematically illustrating a state in which a conductive adhesive layer is formed on a second electrode and a metal pattern thicker than the second electrode is bonded. FIG. 4 is a view schematically illustrating an operation of forming a redistribution layer which electrically connects the semiconductor chip and the light-emitting element. FIG. 5 is a cross-sectional view illustrating a state in which a light-receiving element 300 is arranged on the redistribution layer to be electrically connected to the redistribution layer. FIG. 6 is a view illustrating an outline of a state in which a light-receiving element is arranged on a redistribution layer to be electrically connect