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US-12628695-B2 - Packaging structure and packaging method

US12628695B2US 12628695 B2US12628695 B2US 12628695B2US-12628695-B2

Abstract

This disclosure relates to a packaging structure and a packaging method. The structure includes: a substrate; a first chip, including a first surface and a second surface opposite to each other; a second chip, including a third surface, where the third surface includes a third bonding region bonded to the second bonding region, and a remaining region of the third surface is used as a fourth bonding region; a conductive post, arranged in the fourth bonding region; and a chipset, bonded to the first bonding region of the first chip, where the second bonding region is exposed from a projection of the chipset on the first chip. The chipset includes one or more third chips stacked along a longitudinal direction, adjacent third chips along the longitudinal direction are electrically connected, and the third chip adjacent to the first chip is electrically connected to the first chip.

Inventors

  • Jisong JIN

Assignees

  • SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

Dates

Publication Date
20260512
Application Date
20230112
Priority Date
20220429

Claims (10)

  1. 1 . A packaging structure, comprising: a substrate; a first chip, comprising a first surface and a second surface opposite to each other, wherein the first surface comprises a first bonding region configured to bond to a chipset and a second bonding region configured to bond to a second chip, and the second surface is bonded to the substrate; a second chip, comprising a third surface, wherein the third surface comprises a third bonding region bonded to the second bonding region, and a remaining region of the third surface is used as a fourth bonding region; a conductive post, arranged in the fourth bonding region, wherein an end of the conductive post facing away from the second chip is bonded to the substrate; the chipset, bonded to the first bonding region of the first chip, wherein the second bonding region is exposed from a projection of the chipset on the first chip, the chipset comprises one or more third chips stacked along a longitudinal direction, adjacent third chips along a longitudinal direction are electrically connected, and the third chip adjacent to the first chip is electrically connected to the first chip; and a first packaging layer arranged on the substrate and covering the chipset, a sidewall of the second chip, and the first chip, wherein a bottom surface of the first packaging layer is leveled with the second surface of the first chip and higher than a top surface of the substrate.
  2. 2 . The packaging structure according to claim 1 , wherein the second bonding region is arranged opposite to the third bonding region, and the packaging structure further comprises first conductive bumps arranged between the second bonding region and the third bonding region.
  3. 3 . The packaging structure according to claim 2 , further comprising: a first sealing layer arranged between the second bonding region and the third bonding region and configured to fill a gap between the first conductive bumps and fill a region defined by the fourth bonding region and the conductive post.
  4. 4 . The packaging structure according to claim 1 , further comprising second conductive bumps arranged between the substrate and the second surface of the first chip, and between the substrate and the end of the conductive post facing away from the second chip.
  5. 5 . The packaging structure according to claim 4 , further comprising: a first packaging layer, arranged on the substrate and covering the chipset, a sidewall of the second chip, and the first chip; and a second sealing layer, arranged in a gap between adjacent second conductive bumps between the second surface and the substrate and in a gap between adjacent second conductive bumps between a bottom surface of the first packaging layer and the substrate.
  6. 6 . The packaging structure according to claim 1 , further comprising: third conductive bumps arranged between the first bonding region of the first chip and the chipset.
  7. 7 . The packaging structure according to claim 1 , further comprising: fourth conductive bumps arranged on a surface on a side of the substrate facing away from the first chip.
  8. 8 . The packaging structure according to claim 1 , wherein a ratio of an area of the second bonding region to a total area of the first chip ranges from 5% to 20%.
  9. 9 . The packaging structure according to claim 1 , wherein the first chip is a first logic chip, the second chip is a second logic chip, and the third chip is a memory chip.
  10. 10 . The packaging structure according to claim 1 , further comprising: a thermally conductive layer, arranged on the chipset and on the second chip; and a packaging housing, arranged on the substrate, configured to package the chipset, the second chip, and the first chip, and in contact with the thermally conductive layer.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is based on and claims priority to Chinese patent Application No. 202210466508.5, filed Apr. 29, 2022, the entire content of which is incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to the field of semiconductor packaging, and in particular, to a packaging structure and a packaging method. BACKGROUND A conventional chip manufacturing technology is being pushed to a limit in terms of a size of a single chip. However, applications are eager for a latest technology to realize a large-scale integrated circuit, and it is a challenge to achieve high-speed and small-volume interconnection between chips. A current solution is a relatively small integrated circuit with a silicon bridge (Si bridge) chip being embedded in a silicon substrate. The Si bridge is used to realize interconnection between chips, thereby providing heterogeneous chip packaging. However, current packaging structures are relatively complex, and a speed of communication between chips is to be improved. SUMMARY The forms of the present disclosure provide a packaging structure and a packaging method to improve a speed of communication between chips and optimize performance of the packaging structure. In an aspect of the present disclosure, a packaging structure is provided. The packaging structure may include: a substrate; a first chip, including a first surface and a second surface opposite to each other, the first surface includes a first bonding region configured to bond to a chipset and a second bonding region configured to bond to a second chip, and the second surface is bonded to the substrate; a second chip, including a third surface, the third surface includes a third bonding region bonded to the second bonding region, and a remaining region of the third surface is used as a fourth bonding region; a conductive post, arranged in the fourth bonding region, an end of the conductive post facing away from the second chip is bonded to the substrate; and a chipset, bonded to the first bonding region of the first chip, where the second bonding region is exposed from a projection of the chipset on the first chip, the chipset includes one or more third chips stacked along a longitudinal direction, adjacent third chips along the longitudinal direction are electrically connected, and the third chip adjacent to the first chip is electrically connected to the first chip. In another aspect of the present disclosure, a packaging method is provided. The packaging method may include: providing a carrier substrate; bonding a first chip to the carrier substrate, the first chip includes a first surface and a second surface opposite to each other, and the first surface includes a first bonding region configured to bond to a chipset and a second bonding region configured to bond to a second chip; providing a second chip, the second chip includes a third surface, the third surface includes a third bonding region corresponding to the second bonding region, and a remaining region of the third surface is used as a fourth bonding region; forming a conductive post on the fourth bonding region of the second chip; bonding the third bonding region to the second bonding region, and bonding the conductive post to the carrier substrate, to electrically connect the second chip to the first chip; providing a chipset, the chipset includes one or more third chips stacked along a longitudinal direction, and adjacent third chips along the longitudinal direction are electrically connected; bonding the chipset to the first bonding region, the second bonding region is exposed from a projection of the chipset on the first chip, and the third chip adjacent to the first chip is electrically connected to the first chip; removing the carrier substrate after bonding the third bonding region to the second bonding region and bonding the chipset to the first bonding region; and bonding a substrate to the second surface of the first chip and the conductive post, to electrically connect the substrate to the first chip and the conductive post. Compared with the prior art, the forms of the present disclosure have the following advantages. According to the packaging structure provided in the forms of the present disclosure, the third surface of the second chip includes the third bonding region bonded to the second bonding region, the conductive post is formed in the fourth bonding region on the third surface, the end of the conductive post facing away from the second chip is bonded to the substrate, the chipset is bonded to the first bonding region of the first chip, and the second bonding region is exposed from the projection of the chipset on the first chip. Since the second bonding region is exposed from the projection of the chipset on the first chip, a space can be provided for bonding a part of the second chip to the first chip, so that the part of the second chip can be directly stacked on and bonded t