US-12628697-B2 - Package structure and manufacturing method thereof

Abstract

A package structure and methods for forming the package structure are provided. The package structure includes a package component, an encapsulant disposed around the package component, and a redistribution structure disposed over the package component and the encapsulant. The package component includes a substrate, a protection structure, which includes an organic material, over a first surface of the substrate, and a multi-layered structure encapsulated by the protection structure. Sidewalls of the multi-layered structure are spaced apart from the encapsulant by the protection structure.

Inventors

• Chih-Wei Wu
• Ying-Ching Shih
• Wen-Chih Chiou

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260512

Application Date

20230111

Claims (20)

1. 1 . A method for manufacturing a package structure, comprising: forming a stacked structure over a top surface of a substrate; performing a first singulation process by cutting through the stacked structure at scribe line regions to reveal portions of the top surface of the substrate and form die stacks; forming a protection structure over the substrate, wherein the portions of the top surface of the substrate and sidewalls of the die stacks are covered by the protection structure; performing a second singulation process to cut through the substrate to form package components that each includes one of the die stacks; encapsulating each of the package components with a molding compound; and forming a redistribution structure that is electrically connected to the package components.
2. 2 . The method of claim 1 , wherein forming the protection structure over the substrate comprises: forming a continuous layer that covers the portions of the top surface of the substrate and the die stacks; and performing a planarization process to remove excessive portions from the continuous layer.
3. 3 . The method of claim 2 , wherein forming the protection structure over the substrate further comprises patterning the continuous layer to form a plurality of patterned structures after forming the continuous layer and before performing the planarization process.
4. 4 . The method of claim 3 , wherein the patterned structures each encapsulates one die stack.
5. 5 . A method for manufacturing a package structure, comprising: providing a first die over a first substrate; laterally encapsulating the first die with a first insulation layer over the first substrate; providing a second die over the first die and the first insulation layer; laterally encapsulating the second die with a second insulation layer; forming conductor pillars electrically connected to the first die laterally encapsulated by the first insulation layer; performing a first singulation process by cutting the first insulation layer and the second insulation layer to form die stacks; forming a protection structure, wherein sidewalls of the die stacks are covered by the protection structure; patterning the first substrate to form package components; encapsulating the package components with encapsulations; and forming a redistribution structure over the package components and the encapsulations.
6. 6 . The method of claim 5 further comprising: before forming the conductor pillars, bonding the first die laterally encapsulated by the first insulation layer and the second die laterally encapsulated by the second insulation layer with a second substrate.
7. 7 . The method of claim 6 , wherein the second die and the second insulation layer are in contact with the second substrate after bonding the first die laterally encapsulated by the first insulation layer and the second die laterally encapsulated by the second insulation layer with the second substrate.
8. 8 . The method of claim 6 , wherein the conductor pillars are formed over the first die laterally encapsulated by the first insulation layer after bonding the first die laterally encapsulated by the first insulation layer and the second die laterally encapsulated by the second insulation layer with the second substrate.
9. 9 . The method of claim 6 further comprising: performing a second singulation process after patterning the protection structure, wherein the second singulation process is performed to cut the second substrate to form the package components.
10. 10 . The method of claim 9 , wherein sidewalls of the second substrate laterally offset from sidewalls of the protection structure by a distance after performing a second singulation process.
11. 11 . The method of claim 6 further comprising: sequentially performing a planarization process and a singulation process to pattern patterning the protection structure and the second substrate.
12. 12 . The method of claim 11 , wherein after sequentially performing the planarization process and the singulation process, the conductive pillars are revealed.
13. 13 . The method of claim 11 , wherein after sequentially performing the planarization process and the singulation process, sidewalls of the second substrate are laterally offset from sidewalls of the protection structure.
14. 14 . The method of claim 5 , wherein the protection structure is patterned by exposure and development processes, laser drilling process, photolithography and etching processes, or a combination thereof.
15. 15 . The method of claim 5 further comprising: providing a dummy die aside the second die, wherein the dummy die and the second die are laterally encapsulated by the second insulation layer.
16. 16 . The method of claim 15 , wherein sidewalls of the dummy die are covered by and in contact with the protection structure.
17. 17 . A method for manufacturing a package structure, comprising: providing stacked dies over a substrate; laterally encapsulating the stacked dies with an insulation layer over the substrate; forming conductor pillars electrically connected to the stacked dies laterally encapsulated by the insulation layer; performing a first singulation process by cutting the insulation layer to expose regions of the substrate to form die stacks; forming a protection structure, wherein sidewalls of the die stacks and the regions of the substrate are covered by and in contact with the protection structure; patterning the substrate to form package components; encapsulating the package components with encapsulations; and forming a redistribution structure over the package components and the encapsulations.
18. 18 . The method of claim 17 , wherein forming the protection structure comprises: forming a continuous layer that covers the regions of the substrate and the die stacks; and performing a planarization process to remove excessive portions from the continuous layer.
19. 19 . The method of claim 18 , wherein forming the protection structure over the substrate further comprises: patterning the continuous layer to form a plurality of patterned structures after forming the continuous layer and before performing the planarization process.
20. 20 . The method of claim 19 , wherein the patterned structures each encapsulates one of the die stacks.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority benefit of U.S. provisional application Ser. No. 63/409,218, filed on Sep. 23, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. BACKGROUND The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more of the smaller components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than previous packages. Currently, a technique of integrated fan-out (InFO) packages having more compactness is developed and utilized in various package applications. However, the manufacturing of the semiconductor device in a miniaturized scale becomes more complicated. An increase in a complexity of manufacturing the semiconductor device may cause deficiencies such as delamination of components, or other issues, resulting in a high yield loss of the semiconductor device. As such, there are many challenges for modifying a structure of the semiconductor devices and improving the manufacturing operations. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 through FIG. 10 are schematic cross-sectional views of various stages in a manufacturing method of a package structure in accordance with some embodiments of the disclosure. FIG. 11 is a schematic cross-sectional view showing a package structure in accordance with some embodiments of the disclosure. FIG. 12 through FIG. 14 are schematic cross-sectional views of various stages in a manufacturing method of a package structure in accordance with some embodiments of the disclosure. FIG. 15 is a schematic cross-sectional view showing a package structure in accordance with some embodiments of the disclosure. FIG. 16 through FIG. 20 are schematic cross-sectional views of various stages in a manufacturing method of a package structure in accordance with some embodiments of the disclosure. FIG. 21 is a schematic cross-sectional view showing a package structure in accordance with some embodiments of the disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. FIG. 1 through FIG. 10 are schematic cross-sectional views of various stages in a manufacturing method of a package structure 10A in accordance with some embodiments of the disclosure. It is understood that additional operations can be provided before, during, and after processes shown by FIG. 1 through FIG. 10, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. Referring to FIG. 1, a carrier 50 including a bonding layer 60 formed on a surface thereof is provided. The carrier 50 may be a semiconductor wafer, and