US-12628698-B2 - Multi-layer electronic device interconnection method and structure

US12628698B2US 12628698 B2US12628698 B2US 12628698B2US-12628698-B2

Abstract

An electronic device and a method for manufacturing the same are provided. The electronic device includes an upper electronic structure, an upper connection structure, a first metal layer, a lower electronic structure, a lower connection structure and a second metal layer. The first metal layer electrically connects the upper electronic structure to the upper connection structure. The second metal layer electrically connects the lower electronic structure to the lower connection structure. The upper connection structure and the lower connection structure are bonded together.

Inventors

YU-LUN LU
Kong-Beng Thei

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260512
Application Date: 20230202

Claims (20)

1 . An electronic device, comprising: an upper device layer comprising: a first semiconductor substrate; first semiconductor devices disposed on the first semiconductor substrate; a first back-end-of-line (BEOL) metal interconnect structure disposed on the first semiconductor substrate, wherein the first BEOL metal interconnect structure comprises a plurality of metallization layers interleaved with a plurality of via layers; through silicon vias (TSVs) extending through the first semiconductor substrate and electrically connected to the first BEOL metal interconnect structure; a first bonding layer on the first BEOL metal interconnect structure, wherein the first bonding layer comprises first bond pads electrically connected to the TSVs by first connection structures, wherein the first connection structures are part of the first BEOL metal interconnect structure; a lower device layer comprising: a second semiconductor substrate; second semiconductor devices disposed on the second semiconductor substrate; a second BEOL metal interconnect structure disposed on the second semiconductor substrate, wherein the second BEOL metal interconnect structure comprises a plurality of metallization layers interleaved with a plurality of via layers; and a second bonding layer on the second BEOL metal interconnect structure, wherein the second bonding layer comprises second bond pads bonded to the first bond pads and electrically connected to the second BEOL metal interconnect structure; wherein at least one of the first semiconductor devices is electrically connected to at least one of the second semiconductor devices; all of the first semiconductor devices that are electrically connected to second semiconductor devices are coupled through connections between the first bond pads and the second bond pads; the first semiconductor devices are in a first area of the upper device layer, and the TSVs comprise a grid of TSVs extending across the first area; and the TSVs further comprise TSVs in a row along an edge of the first area, wherein the TSVs in the row along the edge are more closely spaced than the TSVs in the grid.
2 . The electronic device of claim 1 , wherein each of the TSVs in the grid is electrically connected to at least one of the second bond pads.
3 . The electronic device of claim 1 , wherein the second bond pads comprise a grid of bond pads corresponding to the grid of TSVs.
4 . The electronic device of claim 3 , wherein the second bond pads in the grid of bond pads are electrically connected to metal structures that are parts of the second BEOL metal interconnect structure.
5 . The electronic device of claim 1 , wherein: the second BEOL metal interconnect structure comprises a top metallization layer, which is the metallization layer furthest from the second semiconductor substrate; and the top metallization layer includes a connection plate for each of the second bond pads, wherein the connection plates are directly beneath and electrically connected to the corresponding second bond pads.
6 . The electronic device of claim 5 , wherein one of the connection plates has no electrical connections other than to the corresponding second bond pad.
7 . The electronic device of claim 5 , wherein one of the connection plates is part of a metal structure that floats within the second BEOL metal interconnect structure except for being electrically connected to the corresponding second bond pad.
8 . The electronic device of claim 5 , wherein; one of the connections plates is laterally offset from the second semiconductor device; and the first and second semiconductor device are electrically connected through the connections plate that is laterally offset from the second semiconductor device.
9 . The electronic device of claim 1 , wherein; the first connection structures are disposed in the first areas of the upper device layer; and the first connection structures, and lateral connections to the first connection structures, are the only parts of the first BEOL metal interconnect structure disposed in the first areas.
10 . An electronic device, comprising: an upper device layer comprising: a first semiconductor substrate; a first back-end-of-line (BEOL) metal interconnect structure disposed on the first semiconductor substrate, wherein the first BEOL metal interconnect structure comprises a plurality of metallization layers interleaved with a plurality of via layers; through silicon vias (TSVs) extending through the first semiconductor substrate and electrically connected to the first BEOL metal interconnect structure; a first bonding layer on the first BEOL metal interconnect structure, wherein the first bonding layer comprises first bond pads electrically connected to the TSVs by first TSV connection structures which are part of the first BEOL metal interconnect structure; first semiconductor devices disposed on the first semiconductor substrate, wherein the first semiconductor devices have terminals electrically connected to first device connection structures which are part of the first BEOL metal interconnect structure; and first metal connectors that electrically connect the first device connection structures to the first TSV connection structures by making lateral connections between wires in one of the metallization layers in the first BEOL metal interconnect structure; and a lower device layer comprising: a second semiconductor substrate; a second BEOL metal interconnect structure disposed on the second semiconductor substrate, wherein the second BEOL metal interconnect structure comprises a plurality of metallization layers interleaved with a plurality of via layers; a second bonding layer on the second BEOL metal interconnect structure, wherein the second bonding layer comprises second bond pads bonded to the first bond pads and electrically connected to second TSV connection structures which are part of the second BEOL metal interconnect structure; second semiconductor devices disposed on the second semiconductor substrate, wherein the second semiconductor devices have terminals electrically connected to second device connection structures which are part of the second BEOL metal interconnect structure; and second metal connectors that electrically connect the second device connection structures to the second TSV connection structures by making lateral connections between wires in one of the metallization layers in the second BEOL metal interconnect structure; wherein at least one of the first metal connectors or the second metal connectors is distinguished from the wires in the corresponding metallization layer by a difference that establishes the connector was formed separately from the wires in the corresponding metallization layer, wherein the difference is a difference in thickness, composition, or elevation.
11 . The electronic device of claim 10 , wherein both the first and second metal connectors have a difference in elevation, thickness, composition or other feature that establishes they were formed at a separate time from the metallization layer in which they are contained.
12 . The electronic device of claim 10 , wherein the first TSV connection structures are disposed in first areas, the first device connection structures are disposed in second areas, and the first and second areas are non-overlapping areas of the first device layer.
13 . The electronic device of claim 10 , wherein the second TSV connection structures are disposed in first areas, the second device connection structures are disposed in second areas, and the first and second areas are non-overlapping areas of the second device layer.
14 . A method, comprising: providing a first device layer comprising: a first semiconductor substrate; a first back-end-of-line (BEOL) metal interconnect structure disposed on the first semiconductor substrate, wherein the first BEOL metal interconnect structure comprises a plurality of metallization layers interleaved with a plurality of via layers; through silicon vias (TSVs) extending through the first semiconductor substrate and electrically connected to the first BEOL metal interconnect structure; a first bonding layer on the first BEOL metal interconnect structure, wherein the first bonding layer comprises first bond pads electrically connected to the TSVs by first TSV connection structures which are part of the first BEOL metal interconnect structure; and first semiconductor devices disposed on the first semiconductor substrate, wherein the first semiconductor devices have terminals electrically connected to first device connection structures which are part of the first BEOL metal interconnect structure; providing a second device layer comprising: a second semiconductor substrate; a second BEOL metal interconnect structure disposed on the second semiconductor substrate, wherein the second BEOL metal interconnect structure comprises a plurality of metallization layers interleaved with a plurality of via layers; a second bonding layer on the second BEOL metal interconnect structure, wherein the second bonding layer comprises second bond pads bonded to the first bond pads and electrically connected to second TSV connection structures which are part of the second BEOL metal interconnect structure; second semiconductor devices disposed on the second semiconductor substrate, wherein each of the second semiconductor devices has a terminal electrically connected to a corresponding second device connection structure which is part of the second BEOL metal interconnect structure; forming first metal connectors electrically connecting one of the first device connection structures to one of the first TSV connection structures, wherein the first metal connectors are disposed within one of the metallization layers in the first BEOL metal interconnect structure; and forming second metal connectors electrically connecting one of the second device connection structures to one of the second TSV connection structures at an elevation of one of the metallization layers in the second BEOL metal interconnect structure, wherein either the first metal connectors are formed after the first BEOL metal interconnect structure or the second metal connectors are formed after the second BEOL metal interconnect structure; and bonding the first device layer to the second device layer through the first and second bonding layers, wherein the first bond pads are bonded to the second bond pads.
15 . The method of claim 14 , wherein either the first metal connectors are formed after the first BEOL metal interconnect structure or the second metal connectors are formed after the second BEOL metal interconnect structure.
16 . The method of claim 14 , further comprising designing the first and second BEOL metal interconnect structures independently except for a layout of the first and second TSV connection structures.
17 . The method of claim 14 , wherein two or more of the first metal connectors are electrically connected to one of the first TSV connection structures.
18 . The method of claim 14 , wherein two or more of the second metal connectors are electrically connected to one of the second TSV connection structures.
19 . The electronic device of claim 10 , wherein one of the first semiconductor devices is connected to one of the second semiconductor devices through one of the first metal connectors and one of the second metal connectors.
20 . The electronic device of claim 19 , wherein all the first semiconductor devices that are connected to second semiconductor devices are connected through the first metal connectors and the second metal connectors.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63/405,978, filed Sep. 13, 2022, the contents of which are hereby incorporated by reference in their entirety. BACKGROUND As for electronic devices such as multi-stacked devices using wafer-on-wafer (WoW) bonding, face-to-face interconnection can be required for more efficient circuit design and lower resistance, thanks to shorter interconnections. When the circuit design needs to be changed, the original metal line layout becomes an issue. It is difficult to change other metal connections for newly designed circuits through the face-to-face interconnection. If the multi-stacked device is used for function contacts, arranging a reticle field layout (RFL) is also tricky. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure. FIGS. 2A-2D illustrate bottom views of various configurations of contacts and a bottommost circuit layer of the upper connection structure according to some embodiments of the present disclosure. FIG. 3 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure. FIG. 4 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure. FIG. 5 illustrates a schematic layout of an upper portion of an electronic device according to some embodiments of the present disclosure. FIG. 6 illustrates a schematic layout of a lower portion of an electronic device of FIG. 5. FIG. 7 illustrates a schematic layout of an upper portion of an electronic device according to some embodiments of the present disclosure. FIG. 8 illustrates a schematic layout of a lower portion of an electronic device of FIG. 7. FIG. 9 illustrates a schematic layout of an upper portion of an electronic device according to some embodiments of the present disclosure. FIG. 10 illustrates a schematic layout of a lower portion of an electronic device of FIG. 9. FIG. 11 illustrates a cross-sectional view of one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure. FIG. 12 illustrates a cross-sectional view of one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure. FIG. 13 illustrates a cross-sectional view of one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure. FIG. 14 illustrates a cross-sectional view of one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure. FIG. 15 illustrates a cross-sectional view of one or more stages of an example of a method for manufacturing an electronic device according to some embodiments of the present disclosure. FIG. 16 illustrates a flowchart of a method for manufacturing an electronic device according to some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be o