US-12628699-B2 - Packaged electronic device comprising a plurality of power transistors

US12628699B2US 12628699 B2US12628699 B2US 12628699B2US-12628699-B2

Abstract

Electronic device comprising at least a first and a second branch, each branch including a first and a second transistor arranged in series to each other and formed in respective dice of semiconductor material. The dice are sandwiched between a first substrate element and a second substrate element. The first and the second substrate elements are formed each by a multilayer including a first conductive layer, a second conductive layer and an insulating layer extending between the first and the second conductive layers. The first conductive layers of the first and the second substrate elements face towards the outside of the electronic device and define a first and a second main face of the electronic device. The second conductive layer of the first and the second substrate elements is shaped so as to form contact regions facing and in selective electrical contact with the plurality of dice.

Inventors

Cristiano Gianluca STELLA
Agatino Minotti
Francesco Salamone

Assignees

STMICROELECTRONICS S.R.L.

Dates

Publication Date: 20260512
Application Date: 20230323
Priority Date: 20220401

Claims (20)

1 . An electronic device comprising: a bearing structure; a first electronic device including a first main face and a second main face opposite to the first main face; a first height that extends from the first main face to the second main face in a direction directed from the first main face to the second main face; a plurality of bar pins, each respective bar pin of the plurality of bar pins has a bar pin height that extends in the direction, the plurality of bar pins are in direct electrical contact with the bearing structure; a first branch including a first transistor and a second transistor arranged in series; a second branch including a third transistor and a fourth transistor arranged in series; a first substrate element; a second substrate element spaced apart from the first substrate element; and a plurality of dice arranged side by side to each other and between the first and the second substrate elements, the plurality of dice including: a first die including the first transistor of the first branch; a second die including the second transistor of the first branch; a third die including the third transistor of the second branch; and a fourth die including the fourth transistor of the second branch, and wherein the first and the second substrate elements each comprise a multilayer including a first conductive layer, a second conductive layer, and an insulating layer arranged between the first and the second conductive layers, the first conductive layers of the first and the second substrate elements, respectively, face towards an outside of the first electronic device and define the first main face and the second main face, respectively, and the second conductive layers of the first and the second substrate elements include contact regions facing towards the plurality of dice and in selective electrical contact with the plurality of dice; a first cooling structure coupled to the first main face of the first electronic device, the first cooling structure including a second height that extends in the direction; and a second cooling structure coupled to the second main face of the first electronic device, the second cooling structure including a third height that extends in the direction, wherein the bar pin height is equal to a sum of the first height of the first electronic device, the second height of the first cooling structure, and the third height of the second cooling structure.
2 . The electronic device according to claim 1 , further comprising a third branch, the third branch including a fifth transistor and a sixth transistor arranged in series.
3 . The electronic device according to claim 1 , wherein the first branch and the second branch are a full bridge circuit.
4 . The electronic device according to claim 1 , wherein the first and the second substrate elements are formed by-Direct Bonded Copper (DBC) substrates.
5 . The electronic device according to claim 1 , further comprising: a first external terminal; a second external terminal; a third external terminal; and a fourth external terminal, and wherein: the first transistor, the second transistor, the third transistor, and the fourth transistor each have a first conduction terminal, a second conduction terminal, and a control terminal, the second conductive layer of the first substrate element includes: a first connection region coupling the first conduction terminal of the first transistor of the first branch to the first conduction terminal of the third transistor of the second branch, and the first connection region is coupled to the first external terminal; a second connection region coupling the first conduction terminal of the first transistor of the first branch to the second external terminal; and a third connection region coupling the first conduction terminal of the second transistor of the second branch to a third external terminal; the second conductive layer of the second substrate element includes: a fourth connection region coupling the second conduction terminal of the second transistor of the first branch to the second conduction terminal of the fourth transistor of the second branch, and the second connection region is coupled to a fourth external terminal; a fifth connection region coupling the fourth connection region to the second conduction terminal of the first transistor of the first branch; and a sixth connection region coupling the third connection region to the first conduction terminal of the third transistor of the second branch, at least one of the following of the second conductive layers of the first and the second substrate elements including external control regions coupled to the control terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor of the first and the second branches, respectively.
6 . The electronic device according to claim 1 , further comprising: a first external terminal; a second external terminal; and a third external terminal, and wherein: the first transistor, the second transistor, the third transistor, and the fourth transistor have a first conduction terminal, a second conduction terminal, and a control terminal, wherein the second conductive layer of at least one of the following of the first substrate element and the second substrate element includes: a first connection region coupling the first conduction terminal of the first transistor of the first branch to the first conduction terminal of the third transistor of the second branch, and the first connection region is coupled to a first external terminal; a second connection region coupling the second conduction terminal of the first transistor of the first branch to the first conduction terminal of the second transistor of the first branch, and the second connection region is coupled to a second external terminal; a third connection region coupling the second conduction terminal of the first transistor of the second branch to the first conduction terminal of the fourth transistor of the second branch, and the third connection region is coupled to a third external terminal of the electronic device; and a fourth connection region coupling the second conduction terminals of the second transistor of the first branch and the fourth transistor of the second branch to a fourth external terminal of the electronic device; wherein the second conductive layer of at least one of the following of the first substrate element and the second substrate element including external control regions coupled to the control terminals of the first transistor, the second transistor, the third transistor, and the fourth transistor of the first and the second branches, respectively.
7 . The electronic device according to claim 1 , further comprising a packaging mass laterally surrounding the first substrate element, the second substrate element and embedding the plurality of dice, the packaging mass being coplanar with the first conductive layers of the first and the second substrate elements at the first main face and the second main face, respectively.
8 . The electronic device according to claim 1 , comprising external connection leads selectively coupled to the contact regions of the second conductive layer of at least one of the following of the first substrate element and the second substrate element.
9 . The electronic device according to claim 8 , wherein the external connection leads include bar pins for surface mounting having transverse projections in direct electrical contact with selective contact regions.
10 . The electronic device according to claim 9 , wherein a device height extends in a direction directed from the first main face to the second main face and extends from the first main face to the second main face, and the bar pins have a bar pin height that extends in the direction directed from the first main face to the second main face and is greater than the device height.
11 . The device of claim 1 , further comprising a packaging mass on the bar pin.
12 . The device of claim 11 , wherein the packaging mass includes a groove that overlaps the bar pin.
13 . The device of claim 1 , wherein the plurality of bar pins are in electrical communication with at least one of the second conductive layers of the first and second substrate elements.
14 . A power electronic module, comprising: a bearing structure; a first electronic device including: a first main face and a second main face opposite to the first main face, the first main face is on the first cooling structure; a first height that extends from the first main face to the second main face in a direction directed from the first main face to the second main face; bar pins having a bar pin height that extend in the direction directed from the first main face to the second main face; a first branch including a first transistor and a second transistor arranged in series; a second branch including a third transistor and a fourth transistor arranged in series; a first substrate element; a second substrate element spaced apart from the first substrate element; and a plurality of dice arranged side by side to each other and between the first and the second substrate elements, the plurality of dice including: a first die including the first transistor of the first branch; a second die including the second transistor of the first branch; a third die including the third transistor of the second branch; and a fourth die including the fourth transistor of the second branch; a first cooling structure on the first main face of the first electronic device, the first cooling structure having a second height that extends in the direction directed from the first main face to the second main face; and a second cooling structure on the second main face of the first electronic device, the second cooling structure having a third height that extends in the direction directed from the first main face to the second main face; wherein the bar pin height of the bar pins is equal to a sum of the first height of the first electronic device, the second height the first cooling structure, and the third height of the second cooling structure, and the bar pins are in direct electrical contact with the bearing structure; wherein the first and the second substrate elements each comprise a multilayer including a first conductive layer, a second conductive layer and an insulating layer arranged between the first and the second conductive layers, wherein the first conductive layers of the first and the second substrate elements, respectively, face towards an outside of the electronic device and define the first main face and the second main face, respectively, and wherein the second conductive layers of the first and the second substrate elements include contact regions facing towards the plurality of dice and in selective electrical contact with the plurality of dice.
15 . The power electronic module according to claim 14 , further comprising: a second electronic device arranged above the first electronic device and below the first cooling structure; and a third cooling structure arranged between the first and the second electronic devices.
16 . A device, comprising: a bearing structure; a first electronic device including: a first main face and a second main face opposite to the first main face; a first height that extends in a direction from the first main face to the second main face; a first substrate including: a first sidewall; a first surface and a second surface opposite to the first surface, the first surface is at the first main face; a first conductive layer at the first surface; a first insulating layer on the first conductive layer; and a second conductive layer on the first insulating layer and at the second surface; a second substrate including: a second sidewall; a third surface and a fourth surface opposite to the third surface, the third surface faces towards the first substrate and the fourth surface is at the second main face; a third conductive layer at the third surface; a second insulating layer on the second conductive layer; and a fourth conductive layer on the insulating layer and at the fourth surface; a first cooling structure coupled to the first conductive layer of the first substrate and on the first main face, the first cooling structure having a second height that extends in the direction; a second cooling structure opposite to the first cooling structure, the second cooling structure coupled to the fourth conductive layer of the second substrate and on the second main face, the second cooling structure having a third height that extends in the direction; at least one bar pin having a bar pin height that extends in the direction, the at least one bar pin is coupled to the first substrate, the bar pin height of the at least one bar pin is equal to a sum of the first height, the second height, and the third height, the at least one bar pin is in direct electrical contact with the bearing structure; a plurality of dice on the first conductive layer and overlapped by the second conductive layer, the plurality of die being coupled to the first conductive layer and the second conductive layer; and a packaging mass that is between the second surface of the first substrate and the third surface of the second substrate, the packaging mass including: a portion that extends outward from the first and second sidewalls; and a groove that extends into the portion.
17 . The device of claim 16 , wherein the plurality of dice includes: a first branch of dice including: a first die with a first transistor; and a second die with a second transistor, the second transistor being in series with first transistor; a second branch of dice including: a third die with a third transistor; and a fourth die with a fourth transistor, the fourth transistor being in series with the third transistor; a third branch of dice including: a fifth die with a fifth transistor; and a sixth die with a sixth transistor, the sixth transistor being in series with the fifth transistor.
18 . The device of claim 17 , wherein first conduction terminals of the first transistor, the second transistor, and the third transistor are coupled to each other through a first connection region of the third conductive layer of the second substrate, and second conduction terminals of the second transistor, the fourth transistor, and the sixth transistor are coupled to each other through a second connection region of the third conductive layer of the second substrate.
19 . The device of claim 17 , wherein the first conduction terminals of the first transistor, the second transistor, and the third transistor are coupled to each other through a connection region of the second conductive layer of the first substrate.
20 . The device of claim 16 , wherein the packaging mass extends around the first substrate and the second substrate covers the first sidewall of the first substrate and the second sidewall of the second substrate, and the portion of the packaging mass: includes a fifth height that extends in the direction directed from the first surface to the second surface that is equal to the bar pin height.

Description

BACKGROUND Technical Field The present disclosure relates to a packaged electronic device comprising a plurality of power transistors. Description of the Related Art For example, the circuit may comprise power devices operating at high voltage (even up to 1200 V) with currents that may rapidly switch, such as silicon carbide or silicon devices, for example super-junction MOSFETs, IGBTs and gallium nitride (GaN) devices and the like. For such circuits and power electronic devices, particular packages are desired, which allow a high heat dispersion. Such packages are generally formed by insulating rigid bodies, for example of resin, generally of parallelepiped shape, embedding in their interior the electronic component(s), and may comprise a dissipation structure in contact with the electronic component(s), facing the package surface and generally occupying most of a longer base of the parallelepiped shape. The dissipation structure is sometimes formed by the same metal support (called “leadframe”) carrying the die or dice integrating one or more electronic components and a plurality of leads for external connection. Generally, in this case, the leadframe has a surface directly facing the outside of the package. For example, in case of a packaged device comprising a silicon MOSFET transistor, the die integrating the MOSFET transistor may have a drain pad on a first larger surface thereof and at least two contact pads (respectively, source pad and gate pad) on a second larger surface, opposite the first. A transistor contact pad (typically the drain pad) is attached to the leadframe supporting portion, which is in direct contact with one or more leads. The other contact pads (typically, the gate and source pads) are coupled to the other leads through bonding wires or clips. Such a standard package normally has the leads arranged on the same side of the dissipation structure and thus normally allows downward dissipation. Other devices, for example those comprising GaN, have a different external arrangement of the contacts, but still have a conductive rear surface (forming a source contact), and front contact pads for the other terminals. BRIEF SUMMARY The present disclosure is directed to a package allowing upward cooling (TSC—Top Side Cooling), thanks to an appropriate configuration of the lead and leadframe supporting portion. For example, FIG. 1 shows an integrated device 1 comprising two electronic components integrated in respective dice 2A, 2B, and embedded in a packaging insulating mass 3, which has a generally parallelepiped shape, shown in ghost. The integrated device 1 comprises a leadframe 4 formed by a DBC (Direct Bonded Copper) multilayer, comprising a first metal conductive layer, an insulating layer, which is made of ceramic, and a second metal conductive layer. The second metal conductive layer (visible in FIG. 1) is shaped and forms two conductive portions 5A, 5B, electrically separated, forming respective contact portions for the dice 2A, 2B and directly coupled both to respective drain pads (not visible) of the dice 2A, 2B, and to leads 6. Other leads 7 are connected to the source and gate pads of the dice 2A, 2B, as well as to any other contact pads, through conductive regions 9 forming part of the leadframe 4 and, possibly, wires 8. The conductive portions 5A, 5B and 9 are thermally coupled to a thermally dissipative region 10 (FIG. 2A), formed by the first metal conductive layer, facing outwards and level (e.g., coplanar) with the upper face of the packaging insulating mass 3. The conductive portions 5A, 5B and 9 are however electrically separated with respect to the thermally dissipative region 10 thanks to the insulating layer. With this type of package, different circuits and components topologies may be formed, as shown in FIGS. 3A-3I. The integrated device 1 dissipates on one side and may be attached to a dissipation structure, as shown schematically in FIG. 4. Here the integrated device 1 is attached, at its surface opposite to the thermally dissipative region 10 (FIG. 2A), to a support 15, for example a printed circuit board (PCB) through its leads 6, 7 (not visible in FIG. 4). Furthermore, the thermally dissipative region 10 is attached to a heat sinker 16, for example screwed (17) to the support 15. In use, a cooling fluid (air or liquid 18) is flowed in contact with the heat sinker 16. This solution, although allowing an effective cooling on one side, is however not optimal in case of electronic devices formed by components having large dimensions, such as MOSFET transistors having high power and high switching currents, and/or having different topologies. In fact, in this case, the packaged device would have large, unsuitable overall dimensions and still would not have suitable dissipation. To overcome this problem, in Italian patent application 102019000013743 (corresponding to EP 3 780 100), the disclosure is directed to a packaged power electronic device wherein at least two