US-12628706-B2 - Semiconductor package and method of forming same

US12628706B2US 12628706 B2US12628706 B2US 12628706B2US-12628706-B2

Abstract

In an embodiment, a method for manufacturing a semiconductor device includes forming a redistribution structure on a carrier substrate, connecting a plurality of core substrates physically and electrically to the redistribution structure with a first anisotropic conductive film, the first anisotropic conductive film including a dielectric material and conductive particles, and pressing the plurality of core substrates and the redistribution structure together to form conductive paths between the plurality of core substrates and the redistribution structure with the conductive particles in the first anisotropic conductive film. The method also includes encapsulating the plurality of core substrates with an encapsulant. The method also includes and attaching an integrated circuit package to the redistribution structure, the redistribution structure being between the integrated circuit package and the plurality of core substrates, the integrated circuit package laterally overlapping a first core substrate and a second core substrate of the plurality of core substrates.

Inventors

Jiun Yi Wu
Chen-Hua Yu
Chung-Shi Liu

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20230808

Claims (20)

1 . A method, comprising: forming a first redistribution structure on a carrier substrate; connecting a plurality of core substrates to the first redistribution structure with a first anisotropic conductive film, each core substrate of the plurality of core substrates having a first side and a second side, each of the first sides having a second redistribution structure, each of the second sides having a third redistribution structure, each of the plurality of core substrates having a through via extending from the second redistribution structure to the third redistribution structure, the first sides of the plurality of core substrates facing the first redistribution structure, each of the plurality of core substrates having a same top surface area; after connecting the plurality of core substrates to the first redistribution structure with the first anisotropic conductive film, encapsulating the plurality of core substrates with a molding layer, the molding layer extending along and physically contacting sidewalls of the plurality of core substrates and the first anisotropic conductive film, the molding layer physically contacting the first redistribution structure, the molding layer being free from through vias, the molding layer extending along and contacting the second and third redistribution structures of the plurality of core substrates; after encapsulating the plurality of core substrates, removing the carrier substrate; and attaching an integrated circuit package to the first redistribution structure, the first redistribution structure being between the integrated circuit package and the plurality of core substrates, the integrated circuit package laterally overlapping a first core substrate and a second core substrate of the plurality of core substrates.
2 . The method of claim 1 , wherein the first anisotropic conductive film comprises a dielectric material and conductive particles.
3 . The method of claim 2 , wherein the conductive particles of the first anisotropic conductive film comprise copper balls, aluminum balls, nickel balls, or metal-coated polymer balls.
4 . The method of claim 2 , wherein after connecting the plurality of core substrates to the first redistribution structure, pressing the plurality of core substrates and the first redistribution structure together to form conductive paths between the second redistribution structures of the plurality of core substrates and the first redistribution structure with the conductive particles in the first anisotropic conductive film.
5 . The method of claim 4 , wherein before pressing the plurality of core substrates and the first redistribution structure together, the conductive particles of the first anisotropic conductive film did not form conductive paths between the plurality of core substrates and the first redistribution structure.
6 . The method of claim 4 further comprising: at a same time as the pressing the plurality of core substrates and the first redistribution structure together, applying heat to the plurality of core substrates and the first redistribution structure.
7 . The method of claim 1 further comprising: attaching a protective ring to the first redistribution structure, the protective ring encircling the integrated circuit package.
8 . The method of claim 1 further comprising: attaching a printed circuit board to the plurality of core substrates with a second anisotropic conductive film, the plurality of core substrates being between the first and second anisotropic conductive films, the second anisotropic conductive film comprising a dielectric material and conductive particles, the conductive particles of the second anisotropic conductive film forming conductive paths between the printed circuit board and the plurality of core substrates.
9 . The method of claim 1 further comprising: connecting a printed circuit board to the third redistribution structures of the plurality of core substrates with a first set of solder connectors, the first set of solder connectors being directly connected to both the third redistribution structures of the plurality of core substrates and the printed circuit board.
10 . A method for manufacturing a semiconductor device, the method comprising: forming a first redistribution structure on a carrier substrate; after forming the first redistribution structure on the carrier substrate, attaching a plurality of core substrates to the first redistribution structure with a first anisotropic conductive film, each core substrate of the plurality of core substrates having a first side and a second side, each of the first sides having a second redistribution structure, each of the second sides having a third redistribution structure, each of the second and third redistribution structures comprises conductive lines and conductive vias and dielectric layers separating adjacent layers of the conductive lines, the first anisotropic conductive film comprising a dielectric material and conductive particles, the first redistribution structure being between the carrier substrate and the plurality of core substrates, each of the plurality of core substrates having a same top surface area; pressing the plurality of core substrates and the first redistribution structure together to form conductive paths between the second redistribution structures of the plurality of core substrates and the first redistribution structure with the conductive particles in the first anisotropic conductive film; after pressing the plurality of core substrates and the first redistribution structure together, encapsulating the plurality of core substrates with an encapsulant, the encapsulant extending along and contacting the second and third redistribution structures of the plurality of core substrates; after encapsulating the plurality of core substrates, removing the carrier substrate; and after removing the carrier substrate, singulating the first redistribution structure and the encapsulant to form a singulated package component.
11 . The method of claim 10 further comprising: after removing the carrier substrate, attaching an integrated circuit package to the first redistribution structure of the singulated package component, the first redistribution structure being between the integrated circuit package and the plurality of core substrates, the integrated circuit package laterally overlapping a first core substrate and a second core substrate of the plurality of core substrates; and attaching the third redistribution structures of the plurality of core substrates to a printed circuit board with a first set of solder connectors, the first set of solder connectors being directly coupled to both the third redistribution structures of the plurality of core substrates and the printed circuit board.
12 . The method of claim 10 , wherein the encapsulant extends along sidewalls of the plurality of core substrates, the encapsulant being between adjacent ones of the plurality of core substrates.
13 . The method of claim 10 , wherein the conductive particles of the first anisotropic conductive film comprise copper balls, aluminum balls, nickel balls, or metal-coated polymer balls.
14 . The method of claim 10 , wherein before pressing the plurality of core substrates and the first redistribution structure together, the conductive particles of the first anisotropic conductive film did not form conductive paths between the plurality of core substrates and the first redistribution structure.
15 . The method of claim 10 further comprising: at a same time as the pressing the plurality of core substrates and the first redistribution structure together, applying heat to the plurality of core substrates and the first redistribution structure.
16 . The method of claim 10 , wherein the encapsulant physically contacts the plurality of core substrates and the first anisotropic conductive film.
17 . A device, comprising: a first redistribution structure having a first side and a second side; a plurality of core substrates, each core substrate having a first side and a second side, the first side having a second redistribution structure, the second side having a third redistribution structure, each of the second and third redistribution structures comprises conductive lines and conductive vias and dielectric layers separating adjacent layers of the conductive lines, the second redistribution structure being attached to the first side of the first redistribution structure with a first anisotropic conductive film, each of the plurality of core substrates having a same top surface area; a molding layer encapsulating the plurality of core substrates, the molding layer physically contacting the first anisotropic conductive film and the first redistribution structure; an integrated circuit package attached to the second side of the first redistribution structure by first conductive connectors; and a printed circuit board attached to the third redistribution structure of the core substrate with a first set of solder connectors, the first set of solder connectors being coupled to both the third redistribution structure of the core substrate and the printed circuit board.
18 . The device of claim 17 , wherein the molding layer is free from through vias.
19 . The device of claim 17 , wherein the first anisotropic conductive film comprises a dielectric material and conductive particles, the conductive particles of the first anisotropic conductive film forming conductive paths between the first side of the first redistribution structure and the first side of the plurality of core substrates, the conductive particles of the first anisotropic conductive film comprise copper balls, aluminum balls, nickel balls, or metal-coated polymer balls.
20 . The device of claim 17 , wherein the molding layer extends along sidewalls of each of the plurality of core substrates and the first anisotropic conductive film.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a continuation of U.S. patent application Ser. No. 17/187,138, entitled “Semiconductor Package and Method of Forming Same,” filed on Feb. 26, 2021, which application is incorporated herein by reference. BACKGROUND The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged. An example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables production of semiconductor devices with enhanced functionalities and small footprints on a printed circuit board (PCB). BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross-sectional view of a package component in accordance with some embodiments. FIGS. 2 through 15 illustrate cross-sectional views of intermediate steps during a process for forming a package component in accordance with some embodiments. FIG. 16 illustrates a cross-sectional versus a planar view of the layout of multiple core substrates in a package component in accordance with some embodiments. FIGS. 17A, 17B, and 17C illustrate planar views of layouts of multiple core substrates in package components in accordance with some embodiments. FIG. 18 illustrates a cross-sectional view of an intermediate step during a process for forming a package component in accordance with some embodiments. FIGS. 19 through 20 illustrate cross-sectional views of intermediate steps during a process for forming a package component in accordance with some embodiments. FIG. 21 illustrates a planar view of the layout of package regions on a wafer substrate in accordance with some embodiments. FIG. 22 illustrates a planar view of the layout of package regions on a panel substrate in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In accordance with some embodiments, a package component is formed having one or more integrated circuit dies. An anisotropic conductive film (sometimes referred to as an anisotropic conductive elastomer) is formed on the bottom of two or more discrete core substrates. The two or more core substrates are attached, via the anisotropic conductive film, to a redistribution structure build up. Over molding is applied to the RDL build up and two or more core substrates. The one or more integrated circuit dies are attached to the opposite side of the RDL build up as the core substrates, and BGA ball mounting may be performed on the exposed side of the core substr