US-12628709-B2 - Semiconductor package having two-dimensional input and output device

Abstract

A semiconductor package is provided. The semiconductor package includes: a first semiconductor chip including a first bonding structure; a first front-end level layer including a first integrated circuit device; a first sub-back-end level layer including a plurality of first metal wire layers, an input and output device level layer including a two-dimensional input and output device, and a second sub-back-end level layer including a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device. The semiconductor package also includes a second semiconductor chip including a bonding structure that is bonded to the first bonding structure; a second front-end level layer including a second integrated circuit device, and a second back-end level layer including a plurality of third metal wire layers electrically connected to the second integrated circuit device.

Inventors

• Kyungsoo Kim
• KYENHEE LEE

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260512

Application Date

20221102

Priority Date

20220110

Claims (20)

1. 1 . A semiconductor package comprising: a first semiconductor chip comprising: a first bonding structure; a first front-end level layer provided on a first semiconductor substrate and comprising a first integrated circuit device; a first sub-back-end level layer provided on the first front-end level layer and comprising a plurality of first metal wire layers electrically connected to the first integrated circuit device; an input and output device level layer provided on the first sub-back-end level layer and comprising a two-dimensional input and output device; and a second sub-back-end level layer provided on the input and output device level layer and comprising a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device; and a second semiconductor chip comprising: a second bonding structure bonded to the first bonding structure of the first semiconductor chip; a second front-end level layer provided on a second semiconductor substrate and comprising a second integrated circuit device; and a second back-end level layer provided on the second front-end level layer and comprising a plurality of third metal wire layers electrically connected to the second integrated circuit device.
2. 2 . The semiconductor package of claim 1 , wherein the two-dimensional input and output device comprises a two-dimensional channel layer, a gate structure provided on the two-dimensional channel layer, and a source structure and a drain structure, which are provided on the two-dimensional channel layer and respectively on both sides of the gate structure.
3. 3 . The semiconductor package of claim 2 , wherein the two-dimensional channel layer comprises a transition metal di-chalcogenide compound or black phosphorus, and wherein the source structure and the drain structure respectively comprise source and drain dopant layers provided on the two-dimensional channel layer, and source and drain semimetal layers respectively provided on the source and drain dopant layers.
4. 4 . The semiconductor package of claim 1 , wherein the plurality of first metal wire layers and the plurality of second metal wire layers comprise first to fourteenth metal layers sequentially provided on the first semiconductor substrate, and wherein the input and output device level layer is provided between the third metal layer and the seventh metal layer.
5. 5 . The semiconductor package of claim 1 , wherein a number of metal layers provided in the plurality of first metal wire layers and the plurality of second metal wire layers is greater than a number of metal layers provided in the plurality of third metal wire layers.
6. 6 . The semiconductor package of claim 1 , wherein the first integrated circuit device comprises a master device, and the second integrated circuit device comprises a slave device.
7. 7 . The semiconductor package of claim 6 , wherein the master device comprises a processing device, and the slave device comprises a logic device.
8. 8 . The semiconductor package of claim 6 , wherein the master device is a logic device, and the slave device is a processing device or a memory device.
9. 9 . The semiconductor package of claim 1 , wherein the first bonding structure comprises a first through-via structure passing through all of the first sub-back-end level layer, the first front-end level layer, and the first semiconductor substrate, and wherein the second bonding structure comprises a second through-via structure passing through all of the second front-end level layer and the second semiconductor substrate.
10. 10 . The semiconductor package of claim 1 , wherein the first semiconductor chip further comprises a through-via structure passing through all of the second sub-back-end level layer, the input and output device level layer, the first sub-back-end level layer, the first front-end level layer, and the first semiconductor substrate, wherein the first bonding structure comprises a first internal bump provided on the second sub-back-end level layer and the through-via structure, wherein the second bonding structure comprises a second internal bump provided between the second back-end level layer and the first internal bump, and wherein the first internal bump and the second internal bump are bonded to each other.
11. 11 . A semiconductor package comprising: a first semiconductor substrate having a first surface and a second surface opposite to the first surface; a first front-end level layer provided on the first surface of the first semiconductor substrate and comprising a first integrated circuit device; a first sub-back-end level layer provided on the first front-end level layer and comprising a plurality of first metal wire layers electrically connected to the first integrated circuit device; an input and output device level layer provided on the first sub-back-end level layer and comprising a two-dimensional input and output device; a second sub-back-end level layer provided on the input and output device level layer and comprising a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device; a first through-via structure passing through all of the first sub-back-end level layer, the first front-end level layer, and the first semiconductor substrate, along a vertical direction from the input and output device level layer toward the first semiconductor substrate; a second semiconductor substrate having a third surface and a fourth surface opposite to the third surface, wherein the fourth surface is bonded to the second surface of the first semiconductor substrate; a second front-end level layer provided below the third surface of the second semiconductor substrate and comprising a second integrated circuit device; a second back-end level layer provided below the second front-end level layer and comprising a plurality of third metal wire layers electrically connected to the second integrated circuit device; and a second through-via structure bonded to the first through-via structure and passing through all of the second back-end level layer, the second front-end level layer, and the second semiconductor substrate along the vertical direction from the second back-end level layer toward the second semiconductor substrate.
12. 12 . The semiconductor package of claim 11 , wherein the first integrated circuit device comprises a master device, and the second integrated circuit device comprises a slave device.
13. 13 . The semiconductor package of claim 11 , wherein the two-dimensional input and output device comprises a two-dimensional channel layer comprising a transition metal di-chalcogenide compound or black phosphorus, a gate structure provided on the two-dimensional channel layer, and a source structure and a drain structure, which are provided on the two-dimensional channel layer and respectively on both sides of the gate structure.
14. 14 . The semiconductor package of claim 11 , wherein the first sub-back-end level layer further comprises first metal vias connecting the plurality of first metal wire layers to each other, and wherein the second sub-back-end level layer further comprises second metal vias connecting the plurality of second metal wire layers to each other.
15. 15 . The semiconductor package of claim 11 , wherein an upper width of the first through-via structure is less than a lower width of the first through-via structure, and an upper width of the second through-via structure is greater than a lower width of the second through-via structure.
16. 16 . The semiconductor package of claim 11 , further comprising, on the second back-end level layer, an external bump electrically connected to the plurality of second metal wire layers.
17. 17 . A semiconductor package comprising: a first semiconductor substrate having a first surface and a second surface opposite to the first surface; a first front-end level layer provided on the first surface of the first semiconductor substrate and comprising a first integrated circuit device; a first sub-back-end level layer provided on the first front-end level layer and comprising a plurality of first metal wire layers electrically connected to the first integrated circuit device; an input and output device level layer provided on the first sub-back-end level layer and comprising a two-dimensional input and output device; a second sub-back-end level layer provided on the input and output device level layer and comprising a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device; a through-via structure passing through all of the second sub-back-end level layer, the input and output device level layer, the first sub-back-end level layer, the first front-end level layer, and the first semiconductor substrate along a vertical direction from the second sub-back-end level layer toward the first semiconductor substrate; a first bump level layer provided on the second sub-back-end level layer and the through-via structure and comprising a first internal bump; a second semiconductor substrate having a third surface and a fourth surface opposite to the third surface; a second front-end level layer provided below the third surface of the second semiconductor substrate and comprising a second integrated circuit device; a second back-end level layer provided below the second front-end level layer and comprising a plurality of third metal wire layers electrically connected to the second integrated circuit device; and a second bump level layer provided below the second back-end level layer and comprising a second internal bump electrically connected to the plurality of third metal wire layers, wherein the second internal bump is bonded to the first internal bump.
18. 18 . The semiconductor package of claim 17 , wherein the first integrated circuit device comprises a master device, and the second integrated circuit device comprises a slave device.
19. 19 . The semiconductor package of claim 17 , wherein the two-dimensional input and output device comprises a two-dimensional channel layer comprising a transition metal di-chalcogenide compound or black phosphorus, a gate structure provided on the two-dimensional channel layer, and a source structure and a drain structure, which are provided on the two-dimensional channel layer and respectively on both sides of the gate structure.
20. 20 . The semiconductor package of claim 17 , further comprising a wire level layer below the first semiconductor substrate, wherein an external bump electrically connected to the through-via structure is further provided below the wire level layer.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to Korean Patent Application No. 10-2022-0003622, filed on Jan. 10, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package with optimized performance and reduced size. As the amount of data to be processed by electronic devices increases, a semiconductor package with high capacity and high performance is required. In addition, in the semiconductor package, a total area of the package increases due to the increase in the number of integrated semiconductor chips, and the electrical connection between the semiconductor chips become complicated. SUMMARY The present disclosure provides a semiconductor package capable of optimizing performance thereof by facilitating an electrical connection between semiconductor chips while reducing a total area of the semiconductor package. According to an aspect of an example embodiment, a semiconductor package includes: a first semiconductor chip including: a first bonding structure; a first front-end level layer provided on a first semiconductor substrate and including a first integrated circuit device; a first sub-back-end level layer provided on the first front-end level layer and including a plurality of first metal wire layers electrically connected to the first integrated circuit device; an input and output device level layer provided on the first sub-back-end level layer and including a two-dimensional input and output device; and a second sub-back-end level layer provided on the input and output device level layer and including a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device; and a second semiconductor chip including: a second bonding structure bonded to the first bonding structure of the first semiconductor chip; a second front-end level layer provided on a second semiconductor substrate and including a second integrated circuit device; and a second back-end level layer provided on the second front-end level layer and including a plurality of third metal wire layers electrically connected to the second integrated circuit device. According to an aspect of an example embodiment, a semiconductor package includes: a first semiconductor substrate having a first surface and a second surface opposite to the first surface; a first front-end level layer provided on the first surface of the first semiconductor substrate and including a first integrated circuit device; a first sub-back-end level layer provided on the first front-end level layer and including a plurality of first metal wire layers electrically connected to the first integrated circuit device; an input and output device level layer provided on the first sub-back-end level layer and including a two-dimensional input and output device; a second sub-back-end level layer provided on the input and output device level layer and including a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device; a first through-via structure passing through all of the first sub-back-end level layer, the first front-end level layer, and the first semiconductor substrate, along a vertical direction from the input and output device level layer toward the first semiconductor substrate; a second semiconductor substrate having a third surface and a fourth surface opposite to the third surface, wherein the fourth surface is bonded to the second surface of the first semiconductor substrate; a second front-end level layer provided below the third surface of the second semiconductor substrate and including a second integrated circuit device; a second back-end level layer provided below the second front-end level layer and including a plurality of third metal wire layers electrically connected to the second integrated circuit device; and a second through-via structure bonded to the first through-via structure and passing through all of the second back-end level layer, the second front-end level layer, and the second semiconductor substrate along the vertical direction from the second back-end level layer toward the second semiconductor substrate. According to an aspect of an example embodiment, a semiconductor package includes: a first semiconductor substrate having a first surface and a second surface opposite to the first surface; a first front-end level layer provided on the first surface of the first semiconductor substrate and including a first integrated circuit device; a first sub-back-end level layer provided on the first front-end level layer and including a plurality of first metal wire layers electrically connected to the first integrated circuit device; an input and output device level