US-12628710-B2 - Semiconductor package and manufacturing method thereof

US12628710B2US 12628710 B2US12628710 B2US 12628710B2US-12628710-B2

Abstract

The present disclosure is related to a semiconductor package. The semiconductor package includes a substrate and a semiconductor chip. The substrate includes a window through a center portion of the substrate, in which the substrate has an inner sidewall surrounding the window and a conductive foil located on a top surface of the substrate, in which the conductive foil extends beyond the inner sidewall of the substrate. The semiconductor chip is located on the top surface of the substrate, in which the conductive foil is located between the substrate and the semiconductor chip, and the semiconductor chip has a bonding pad electrically connected to the conductive foil.

Inventors

Wu-Der Yang

Assignees

NANYA TECHNOLOGY CORPORATION

Dates

Publication Date: 20260512
Application Date: 20221114

Claims (12)

1 . A semiconductor package, comprising: a substrate, comprising: a window through a center portion of the substrate, wherein the substrate has an inner sidewall surrounding the window; and a conductive foil located on a top surface of the substrate, wherein the conductive foil extends beyond the inner sidewall of the substrate, the conductive foil has a horizontal portion in direct physical contact and vertically overlapping the top surface of the substrate, and there is no molding compound between the horizontal portion of the conductive foil and the top surface of the substrate; and a semiconductor chip located on the top surface of the substrate, wherein the conductive foil is located between the substrate and the semiconductor chip, and the semiconductor chip has a bonding pad electrically connected to the conductive foil.
2 . The semiconductor package of claim 1 , further comprising: a molding compound located on the top surface of the substrate and surrounds the semiconductor chip.
3 . The semiconductor package of claim 2 , wherein the molding compound has a portion covering a top surface of the semiconductor chip.
4 . The semiconductor package of claim 1 , further comprising: a molding compound located in the window of the substrate and extending to a bottom surface of the substrate.
5 . The semiconductor package of claim 4 , wherein the molding compound is in contact with the conductive foil and the bonding pad.
6 . The semiconductor package of claim 1 , wherein a portion of the conductive foil and the bonding pad are directly above the window of the substrate.
7 . The semiconductor package of claim 1 , further comprising: an adhesive layer located between the semiconductor chip and the substrate.
8 . The semiconductor package of claim 7 , wherein the adhesive layer is located on the top surface of the substrate and surrounds the window.
9 . The semiconductor package of claim 7 , wherein the adhesive layer is in contact with the conductive foil of the substrate.
10 . The semiconductor package of claim 1 , wherein the substrate further comprises: a conductive via located in the substrate and through the top surface of the substrate and a bottom surface of the substrate.
11 . The semiconductor package of claim 10 , wherein a top end of the conductive via is electrically connected to the conductive foil.
12 . The semiconductor package of claim 10 , wherein the substrate further comprises a conductive region electrically connected to a bottom end of the conductive via, and the semiconductor package further comprises: a solder ball located on the conductive region.

Description

BACKGROUND Field of Invention The present disclosure relates to a semiconductor package and a manufacturing method of the semiconductor package. Description of Related Art As the data rate of DRAM (dynamic random access memory) rises significantly while entering the era of DDR5 SDRAM (double data rate fifth-generation synchronous DRAM). The data rate is going to rise up to 8000 MHz (Mega Hertz). A traditional wBGA (window ball grid array) package using bonding wires to electrically connect DRAM chip and PCB (Printed circuit board) substrate is not capable to work at such high data rate. The general solution of this problem is to use flip-chip BGA (ball grid array) package to package the memory. However, the formation of the flip-chip BGA includes a step in which copper pillars must be formed by additional semiconductor manufacturing process before packaging, which results in a long cycle time of packaging and the raise of the cost in the packaging process. SUMMARY One aspect of the present disclosure provides a semiconductor package. According to one embodiment of the present disclosure, a semiconductor package includes a substrate and a semiconductor chip. The substrate includes a window through a center portion of the substrate, in which the substrate has an inner sidewall surrounding the window, and a conductive foil located on a top surface of the substrate, in which the conductive foil extends beyond the inner sidewall of the substrate. The semiconductor chip is located on the top surface of the substrate, in which the conductive foil is located between the substrate and the semiconductor chip, and the semiconductor chip has a bonding pad and is electrically connected to the conductive foil. In some embodiments of the present disclosure, the semiconductor package further includes a molding compound located on the top surface of the substrate and surrounds the semiconductor chip. In some embodiments of the present disclosure, the molding compound has a portion covering a top surface of the semiconductor chip. In some embodiments of the present disclosure, the semiconductor package further includes a molding compound located in the window of the substrate and extending to a bottom surface of the substrate. In some embodiments of the present disclosure, the molding compound is in contact with the conductive foil and the bonding pad. In some embodiments of the present disclosure, a portion of the conductive foil and the bonding pad are directly above the window of the substrate. In some embodiments of the present disclosure, the semiconductor package further includes an adhesive layer located between the semiconductor chip and the substrate. In some embodiments of the present disclosure, the adhesive layer is located on the top surface of the substrate and surrounds the window. In some embodiments of the present disclosure, the adhesive layer is in contact with the conductive foil of the substrate. In some embodiments of the present disclosure, in which the substrate further includes a conductive via located in the substrate and through the top surface of the substrate and the bottom surface of the substrate. In some embodiments of the present disclosure, in which a top end of the conductive via is electrically connected to the conductive foil. In some embodiments of the present disclosure, in which the substrate further includes a conductive region electrically connected to a bottom end of the conductive via, and the semiconductor package further includes a solder ball located on the conductive region. Another aspect of the present disclosure provides a manufacturing method of a semiconductor package. According to one embodiment of the present disclosure, a manufacturing method of a semiconductor package includes: forming a window through a center portion of a substrate, such that the substrate has an inner sidewall surrounds the window, in which the substrate has a conductive foil located on a first surface of the substrate and extending beyond the inner sidewall of the substrate; attaching the substrate to the first surface of the semiconductor chip such that the conductive foil is located between the substrate and the semiconductor chip; and soldering the conductive foil of the substrate to a bonding pad of the semiconductor chip such that the bonding pad of the semiconductor chip is electrically connected to the conductive foil. In some embodiments of the present disclosure, The manufacturing method of a semiconductor package further includes: forming a first portion of a molding compound on the first surface of the substrate and a second portion of the molding compound in the window of the substrate, in which the first portion of the molding compound surrounds the semiconductor chip and covers the semiconductor chip, and the second portion of the molding compound extends to a second surface of the substrate opposite the first surface of the substrate. In some embodiments of the present disclosure, th