US-12628712-B2 - Semiconductor package having protrusions from redistribution wiring layer and method of manufacturing the semiconductor package

US12628712B2US 12628712 B2US12628712 B2US 12628712B2US-12628712-B2

Abstract

A semiconductor package includes a first redistribution wiring layer having a first surface and a second surface opposite to the first surface, the first redistribution wiring layer having protrusions protruding from the first surface and a plurality of first bonding pads provided on the protrusions, a first semiconductor device mounted on the first redistribution wiring layer via conductive bumps, a plurality of conductive structures respectively extending from the first bonding pads around the first semiconductor device, and a second redistribution wiring layer disposed on the conductive structures and electrically connected to the first redistribution wiring layer.

Inventors

JAEKYUNG YOO
Woohyeong KIM
Jinwoo Park
JUHYEON OH
Jayeon LEE

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260512
Application Date: 20230324
Priority Date: 20220907

Claims (20)

1 . A semiconductor package, comprising: a first redistribution wiring layer having a first surface and a second surface opposite to the first surface, the first redistribution wiring layer comprising protrusions protruding from the first surface and a plurality of first bonding pads provided on the protrusions, the first redistribution wiring layer comprising a plurality of insulating layers in which each insulating layer has a shape correspond to a shape of the protrusions; a first semiconductor device mounted on the first redistribution wiring layer via conductive bumps; a plurality of conductive structures respectively extending from the plurality of first bonding pads around the first semiconductor device; and a second redistribution wiring layer disposed on the plurality of conductive structures and electrically connected to the first redistribution wiring layer.
2 . The semiconductor package of claim 1 , wherein a height of the plurality of conductive structures is in a range of from 50 μm to 200 μm.
3 . The semiconductor package of claim 1 , further comprising: a second semiconductor device on the second redistribution wiring layer.
4 . The semiconductor package of claim 1 , further comprising: a molding member between the first redistribution wiring layer and the second redistribution wiring layer, and provided on the first semiconductor device and the plurality of conductive structures.
5 . The semiconductor package of claim 1 , wherein the protrusions protrude from the first surface to a predetermined height, and wherein the predetermined height is in a range of from 150 μm to 300 μm.
6 . The semiconductor package of claim 1 , wherein the first redistribution wiring layer comprises at least one cavity provided on the second surface.
7 . The semiconductor package of claim 6 , wherein the first redistribution wiring layer further comprises a second bonding pad exposed from a bottom surface of the at least one cavity, and wherein the semiconductor package further comprises a passive element bonded to the second bonding pad and electrically connected to the first redistribution wiring layer.
8 . The semiconductor package of claim 1 , wherein the first redistribution wiring layer further comprises a plurality of redistribution wirings electrically connecting the first semiconductor device and the plurality of conductive structures, and wherein the plurality of redistribution wirings comprise a redistribution via and a redistribution line on the redistribution via.
9 . The semiconductor package of claim 8 , wherein a first bonding pad from the plurality of first bonding pads is provided on the redistribution line.
10 . The semiconductor package of claim 8 , wherein a first bonding pad from the plurality of first bonding pads is provided on the redistribution via.
11 . The semiconductor package of claim 8 , wherein at least one of the plurality of redistribution wirings extends on the first surface to varying heights in a thickness direction of the first redistribution wiring layer at the protrusions.
12 . The semiconductor package of claim 8 , wherein the plurality of conductive structures comprise at least one of nickel (Ni), antimony (Sb), bismuth (Bi), zinc (Zn), indium (In), palladium (Pd), platinum (Pt), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), gold (Au), silver (Ag), chromium (Cr), and tin (Sn).
13 . A method of manufacturing a semiconductor package, the method comprising: forming insulating layers and redistribution wirings on a block layer to form a first redistribution wiring layer comprising protrusions protruding upward, the first redistribution wiring layer comprising a plurality of insulating layers in which each insulating layer has a shape correspond to a shape of the protrusions; providing a plurality of first bonding pads on the protrusions; forming a plurality of conductive structures that extend from the plurality of first bonding pads, respectively; disposing a first semiconductor device on the first redistribution wiring layer via conductive bumps; forming a molding member on the first semiconductor device and at least one conductive structure from among the plurality of conductive structures; and forming a second redistribution wiring layer on the molding member to be electrically connected to end portions of the plurality of conductive structures exposed from the molding member.
14 . The method of claim 13 , wherein forming the plurality of conductive structures further comprises forming the plurality of conductive structures to extend to a predetermined height, and wherein the predetermined height is in a range of from 50 μm to 200 μm.
15 . The method of claim 13 , wherein forming the first redistribution wiring layer comprises forming the protrusions to protrude to a predetermined height, and wherein the predetermined height is in a range of from 150 μm to 300 μm.
16 . The method of claim 13 , the method further comprising: disposing a second semiconductor device on the second redistribution wiring layer so as to be electrically connected to the first semiconductor device through the plurality of conductive structures.
17 . The method of claim 13 , the method further comprising: removing the block layer from the first redistribution wiring layer.
18 . The method of claim 13 , wherein forming the first redistribution wiring layer further comprises disposing a second bonding pad on the block layer to be exposed from the first redistribution wiring layer.
19 . The method of claim 18 , further comprising: bonding a passive element on the second bonding pad to electrically connect to the first semiconductor device.
20 . A semiconductor package, comprising: a first redistribution wiring layer having a first surface and a second surface opposite to the first surface, the first redistribution wiring layer comprising first bonding pads provided in a chip mounting region of the first surface, protrusions protruding from the first surface in an outer region around the chip mounting region, and second bonding pads respectively provided on upper surfaces of the protrusions, the first redistribution wiring layer comprising a plurality of insulating layers in which each insulating layer has a shape correspond to a shape of the protrusions; a first semiconductor device disposed on the chip mounting region on the first redistribution wiring layer, the first semiconductor device mounted via conductive bumps that are disposed on the first bonding pads; a sealing member on the first surface of the first redistribution wiring layer and disposed on the first semiconductor device; a plurality of conductive structures respectively extending from the second bonding pads to penetrate the sealing member; and a second redistribution wiring layer disposed on the sealing member, the second redistribution wiring layer electrically connected to the plurality of conductive structures.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to Korean Patent Application No. 10-2022-0113505, filed on Sep. 7, 2022, in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated by reference herein in its entirety. BACKGROUND 1. Field The disclosure relates to a semiconductor package and a method of manufacturing the semiconductor package. More particularly, example embodiments relate to a semiconductor package including a plurality of stacked different semiconductor devices and a method of manufacturing the same. 2. Description of Related Art In manufacturing a fan-out wafer-level package (FOWLP), a conductive structure (Cu Post) may be used to connect a lower redistribution wiring layer on which a first semiconductor device is mounted and an upper redistribution wiring layer on which a second semiconductor device is mounted. As heights of the conductive structures increase, the deviation of the heights, for example, dispersion may increase, and accordingly a process difficulty and process time may increase. SUMMARY One or more example embodiments provide a semiconductor package including a redistribution wiring layer having a structure that reduces process difficulty and process time for forming conductive structures and a method of manufacturing the semiconductor package. According to an example embodiment, a semiconductor package includes: a first redistribution wiring layer having a first surface and a second surface opposite to the first surface, the first redistribution wiring layer comprising protrusions protruding from the first surface and a plurality of first bonding pads provided on the protrusions; a first semiconductor device mounted on the first redistribution wiring layer via conductive bumps; a plurality of conductive structures respectively extending from the plurality of first bonding pads around the first semiconductor device; and a second redistribution wiring layer disposed on the plurality of conductive structures and electrically connected to the first redistribution wiring layer. According to an aspect of an example embodiment, a method of manufacturing a semiconductor package includes: forming insulating layers and redistribution wirings on a block layer to form a first redistribution wiring layer comprising protrusions protruding upward; providing a plurality of first bonding pads on the protrusions; forming a plurality of conductive structures that extend from the plurality of first bonding pads, respectively; disposing a first semiconductor device on the first redistribution wiring layer via conductive bumps; forming a molding member on the first semiconductor device and the conductive structure; and forming a second redistribution wiring layer on the molding member to be electrically connected to end portions of the plurality of conductive structures exposed from the molding member. According to an aspect of an example embodiment, a semiconductor package includes: a first redistribution wiring layer having a first surface and a second surface opposite to the first surface, the first redistribution wiring layer comprising first bonding pads provided in a chip mounting region of the first surface, protrusions protruding from the first surface in an outer region around the chip mounting region, and second bonding pads respectively provided on upper surfaces of the protrusions; a first semiconductor device disposed on the chip mounting region on the first redistribution wiring layer, the first semiconductor device mounted via conductive bumps that are disposed on the first bonding pads; a sealing member on the first surface of the first redistribution wiring layer and disposed on the first semiconductor device; a plurality of conductive structures respectively extending from the second bonding pads to penetrate the sealing member; and a second redistribution wiring layer disposed on the sealing member, the second redistribution wiring layer electrically connected to the plurality of conductive structures. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects and features will be more apparent from the following description of example embodiments, taken in conjunction with the accompanying drawings, in which: FIG. 1 is a cross-sectional view illustrating a semiconductor package in accordance with example embodiments. FIG. 2 is an enlarged cross-sectional view illustrating portion ‘A’ in FIG. 1. FIGS. 3 to 14 are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with example embodiments. FIG. 15 is a plan view illustrating a semiconductor package having a modified redistribution wiring layer in accordance with example embodiments. FIGS. 16 to 20 are cross-sectional views illustrating a method of manufacturing a semiconductor package in FIG. 15 in accordance with example embodiments. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS Example embodiments will be described more fully w