US-12628713-B2 - Giga interposer integration through chip-on-wafer-on-substrate

Abstract

A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Inventors

• Shang-Yun Hou
• Chi-Hsi Wu
• Chen-Hua Yu
• Hsien-Pin Hu
• Sao-Ling Chiu
• Wen-Hsin Wei
• Ping-Kang Huang
• Chih-Ta SHEN
• Szu-Wei Lu
• Ying-Ching Shih
• Wen-Chih Chiou

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260512

Application Date

20240319

Claims (20)

1. 1 . A semiconductor structure comprising: a redistribution structure; a first interposer on the redistribution structure; a second interposer on the redistribution structure and laterally adjacent to the first interposer, wherein a conductive line of the redistribution structure extends continuously from the first interposer to the second interposer; a first molding material on the redistribution structure around the first interposer and around the second interposer; a first die attached to a first side of the first interposer and attached to a first side of the second interposer; an underfill material between the first interposer and the first die and between the second interposer and the first die, wherein the first molding material surrounds the underfill material, wherein the first molding material and the underfill material have a coplanar surface; and a second molding material around the first die, wherein the second molding material contacts the coplanar surface.
2. 2 . The semiconductor structure of claim 1 , wherein the first molding material contacts and extends along a sidewall of the underfill material.
3. 3 . The semiconductor structure of claim 2 , further comprising a second die attached to the first side of the second interposer, wherein the second die is disposed within lateral extents of the second interposer and is surrounded by the second molding material.
4. 4 . The semiconductor structure of claim 1 , wherein a width of the underfill material, measured between opposing sidewalls of the underfill material, increases as the underfill material extends away from the redistribution structure.
5. 5 . The semiconductor structure of claim 1 , wherein the first molding material and the second molding material have a same width such that sidewalls of the first molding material are aligned with respective sidewalls of the second molding material.
6. 6 . The semiconductor structure of claim 5 , wherein the first molding material and the redistribution structure have a same width such that the sidewalls of the first molding material are aligned with respective sidewalls of the redistribution structure.
7. 7 . The semiconductor structure of claim 1 , further comprising: conductive bumps at a first side of the redistribution structure facing away from the first interposer; and a substrate attached to the conductive bumps.
8. 8 . The semiconductor structure of claim 7 , further comprising another underfill material between the redistribution structure and the substrate.
9. 9 . The semiconductor structure of claim 8 , wherein the another underfill material extends from the substrate, along a first sidewall of the first molding material, to a second sidewall of the second molding material.
10. 10 . A semiconductor structure comprising: a first interposer and a second interposer laterally adjacent to the first interposer, wherein the first interposer and the second interposer are physically separated; a first molding material around the first interposer and the second interposer; a first die bonded to the first interposer and bonded to the second interposer; an underfill material between the first die and the first interposer, wherein the first molding material surrounds the underfill material, wherein the first molding material and the underfill material have a coplanar upper surface facing the first die; and a second molding material over the first molding material and over the underfill material, wherein the second molding material surrounds the first die, wherein a thickness of the underfill material, measured between opposing sidewalls of the underfill material, increases as the underfill material extends from the first interposer toward the first die.
11. 11 . The semiconductor structure of claim 10 , wherein the second molding material contacts and extends along the coplanar upper surface.
12. 12 . The semiconductor structure of claim 10 , wherein the first molding material contacts and extends along the opposing sidewalls of the underfill material.
13. 13 . The semiconductor structure of claim 10 , further comprising a redistribution structure at a first side of the first interposer and at a first side of the second interposer, wherein the first side of the first interposer faces away from the first die, wherein the redistribution structure extends continuously from the first interposer to the second interposer.
14. 14 . The semiconductor structure of claim 13 , wherein the first molding material and the redistribution structure have a same width such that sidewalls of the first molding material are aligned with respective sidewalls of the redistribution structure.
15. 15 . The semiconductor structure of claim 13 , further comprising: conductive bumps at a first side of the redistribution structure facing away from the first interposer; and a substrate attached to the conductive bumps.
16. 16 . A semiconductor structure comprising: a substrate; a redistribution structure, wherein a first side of the redistribution structure is attached to the substrate; a first interposer and a second interposer attached to an opposing second side of the redistribution structure, wherein the first interposer is spaced apart from the second interposer; a first die bonded to the first interposer and the second interposer; a first underfill material between the first interposer and the first die and between the second interposer and the first die, wherein a first width of the first underfill material, measured between opposing sidewalls of the first underfill material, increases as the first underfill material extends away from the substrate; a first molding material on the redistribution structure, wherein the first molding material surrounds the first interposer, the second interposer, and the first underfill material; and a second molding material on the first molding material and around the first die, wherein the first molding material and the first underfill material have a coplanar surface facing the second molding material.
17. 17 . The semiconductor structure of claim 16 , further comprising a second underfill material between the redistribution structure and the substrate, wherein the second underfill material extends along the opposing sidewalls of the first molding material and along sidewalls of the second molding material, wherein a second width of the second underfill material, measured between opposing sidewalls of the second underfill material, decreases as the second underfill material extends away from the substrate.
18. 18 . The semiconductor structure of claim 16 , wherein the first underfill material comprises a polymer.
19. 19 . The semiconductor structure of claim 18 , wherein the second molding material extends along the coplanar surface.
20. 20 . The semiconductor structure of claim 16 , wherein the first underfill material fills a first portion of a gap between the first interposer and the second interposer, and the first molding material fills a second portion of the gap between the first interposer and the second interposer.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a continuation of U.S. patent application Ser. No. 17/870,099, filed on Jul. 21, 2022 and entitled “Giga Interposer Integration through Chip-On-Wafer-On-Substrate,” which is a divisional of U.S. patent application Ser. No. 16/881,211, filed on May 22, 2020 and entitled “Giga Interposer Integration through Chip-On-Wafer-On-Substrate,” now U.S. Pat. No. 11,728,254 issued on Aug. 15, 2023, which applications are incorporated herein by reference. TECHNICAL FIELD The present invention relates generally to semiconductor packages, and, in particular embodiments, to Chip-On-Wafer-On-Substrate (CoWoS) packages and methods for forming CoWoS packages. BACKGROUND The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices has grown, a need for smaller and more creative packaging techniques of semiconductor dies has emerged. An example of such packaging systems is Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. Another example is a Chip-On-Wafer-On-Substrate (CoWoS) structure, where a semiconductor chip is attached to a wafer (e.g., an interposer) to form a Chip-On-Wafer (CoW) structure. The CoW structure is then attached to a substrate (e.g., a printed circuit board) to form a CoWoS structure. These and other advanced packaging technologies enable production of semiconductor devices with enhanced functionalities and small footprints. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIGS. 1-4, 5A and 5B illustrate various views of a Chip-On-Wafer (CoW) device at various stages of fabrication, in an embodiment; FIG. 6 illustrates a cross-sectional view of a Chip-On-Wafer-On-Substrate (CoWoS) device, in an embodiment; FIG. 7 illustrates a cross-sectional view of a CoWoS device, in another embodiment; FIGS. 8 and 9 illustrate cross-sectional views of a CoW device at various stages of fabrication, in an embodiment; FIG. 10 illustrates a cross-sectional view of a CoWoS device, in an embodiment; FIGS. 11-17 illustrate various embodiment cross-sectional views of a front-side portion of an interposer, in some embodiments; FIGS. 18 and 19 illustrate various embodiment cross-sectional views of a backside portion of an interposer, in some embodiments; and FIG. 20 is a flow chart of method for forming a semiconductor structure, in some embodiments. DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Throughout the description herein, unless otherwise described, the same reference number in different figures refers to the same or similar component formed by a same or similar process using a same or similar material(s). In some embodiments, a CoW device includes a plurality of dies attached to a first interposer and to a second interposer. The second interposer is spaced apart from the first interposer, and is positioned side-by-side with the first interposer. The first interposer and the second interposer are embedded in first molding material. A redistribution structure may be formed alon