US-12628715-B2 - Semiconductor device

US12628715B2US 12628715 B2US12628715 B2US 12628715B2US-12628715-B2

Abstract

A semiconductor device includes: a first chip mounting portion and a second chip mounting portion adjacent to each other in a first direction; a first semiconductor chip and a third semiconductor chip adjacent to each other in a second direction and mounted on the first chip mounting portion; and a second semiconductor chip mounted on the second chip mounting portion. The third semiconductor has: one or more first transformers used to transmit a signal from the first semiconductor chip to the second semiconductor chip; and one or more second transformers used to transmit a signal from the second semiconductor chip to the first semiconductor chip. In plan view, the first and second transformers are arranged along a side facing the second semiconductor chip, and the one of more first transformers are arranged closer to the first semiconductor chip than the one of more second transformers.

Inventors

Takamichi Hosokawa
Tatsuaki Tsukuda
Yoshihiro Masumura

Assignees

RENESAS ELECTRONICS CORPORATION

Dates

Publication Date: 20260512
Application Date: 20231006
Priority Date: 20221219

Claims (18)

1 . A semiconductor device comprising: a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; a second semiconductor chip mounted on the second chip mounting portion; a third semiconductor chip mounted on the first chip mounting portion and having a plurality of transformers; and a sealing body sealing the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first chip mounting portion and the second chip mounting portion, wherein each of the plurality of transformers has a primary coil and a secondary coil that are magnetically coupled to each other, wherein the first chip mounting portion and the second chip mounting portion are adjacent to each other in a first direction, wherein the first semiconductor chip and the third semiconductor chip are adjacent to each other in a second direction that is perpendicular to the first direction, wherein, in plan view, the third semiconductor chip has: a third side facing a first side of the first semiconductor chip; and a fourth side facing a second side of the second semiconductor chip, wherein, in plan view, the plurality of transformers is arranged along the fourth side of the third semiconductor chip, wherein the first semiconductor chip has: a plurality of first transmitting pads electrically connected with a first transmitting circuit formed in the first semiconductor chip; and a plurality of first receiving pads electrically connected with a first receiving circuit formed in the first semiconductor chip, wherein the second semiconductor chip has: a plurality of second transmitting pads electrically connected with a second transmitting circuit formed in the second semiconductor chip; and a plurality of second receiving pads electrically connected with a second receiving circuit formed in the second semiconductor chip, wherein the plurality of transformers of the third semiconductor chip has: at least one or more first transformers used to transmit a signal from the first semiconductor chip to the second semiconductor chip; and at least one or more second transformers used to transmit a signal from the second semiconductor chip to the first semiconductor chip, wherein the primary coil of the one or more first transformers is electrically connected with the plurality of first transmitting pads of the first semiconductor chip, wherein the secondary coil of the one or more first transformers is electrically connected with the plurality of second receiving pads of the second semiconductor chip, wherein the primary coil of the one or more second transformers is electrically connected with the plurality of second transmitting pads of the second semiconductor chip, wherein the secondary coil of the one or more second transformers is electrically connected with the plurality of first receiving pads of the first semiconductor chip, wherein, in plan view, the one or more first transformers are arranged closer to the first semiconductor chip than the one or more second transformers, and wherein, in plan view, the plurality of first transmitting pads is arranged closer to the second semiconductor chip than the plurality of first receiving pads.
2 . The semiconductor device according to claim 1 , wherein, in plan view, the plurality of first transmitting pads and the plurality of first receiving pads are arranged along the first side of the first semiconductor chip.
3 . The semiconductor device according to claim 2 , wherein, in plan view, the plurality of second transmitting pads and the plurality of second receiving pads are arranged along the second side of the second semiconductor chip.
4 . The semiconductor device according to claim 3 , wherein, in plan view, the plurality of second receiving pads is arranged closer to the first semiconductor chip than the plurality of second transmitting pads.
5 . The semiconductor device according to claim 1 , wherein a number of the one or more second transformers is larger than a number of the one or more first transformers.
6 . The semiconductor device according to claim 1 , further comprising: a plurality of leads; and a plurality of wires, wherein the sealing body seals a portion of each of the plurality of leads and the plurality of wires.
7 . The semiconductor device according to claim 6 , wherein the third semiconductor chip has: a plurality of first pads electrically connected with the primary coil of the one or more first transformers; a plurality of second pads electrically connected with the secondary coil of the one or more first transformers; a plurality of third pads electrically connected with the primary coil of the one or more second transformers; and a plurality of fourth pads electrically connected with the secondary coil of the one or more second transformers, and wherein the plurality of wires includes: a plurality of first wires electrically connecting the plurality of first transmitting pads with the plurality of first pads, respectively; a plurality of second wires electrically connecting the plurality of second receiving pads with the plurality of second pads, respectively; a plurality of third wires electrically connecting the plurality of second transmitting pads with the plurality of third pads, respectively; and a plurality of fourth wires electrically connecting the plurality of first receiving pads with the plurality of fourth pads, respectively.
8 . The semiconductor device according to claim 7 , wherein the first semiconductor chip further has a plurality of fifth pads, wherein the second semiconductor chip further has a plurality of sixth pads, wherein the plurality of wires further includes: a plurality of fifth wires electrically connecting the plurality of fifth pads with a plurality of first leads of the plurality of leads, respectively; and a plurality of sixth wires electrically connecting the plurality of sixth pads with a plurality of second leads of the plurality of leads, respectively.
9 . The semiconductor device according to claim 1 , wherein the plurality of second transmitting pads is electrically connected with the primary coil of the one or more second transformers, respectively; and wherein the plurality of first receiving pads is electrically connected with the secondary coil of the one or more second transformers, respectively.
10 . A semiconductor device comprising: a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; a second semiconductor chip mounted on the second chip mounting portion; a third semiconductor chip mounted on the first chip mounting portion and having a plurality of transformers; and a sealing body sealing the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first chip mounting portion and the second chip mounting portion, wherein each of the plurality of transformers has a primary coil and a secondary coil that are magnetically coupled to each other, wherein the first chip mounting portion and the second chip mounting portion are adjacent to each other in a first direction, wherein the first semiconductor chip and the third semiconductor chip are adjacent to each other in a second direction that is perpendicular to the first direction, wherein, in plan view, the third semiconductor chip has: a third side facing a first side of the first semiconductor chip; and a fourth side facing a second side of the second semiconductor chip, wherein, in plan view, the plurality of transformers is arranged along the third side of the third semiconductor chip, wherein the first semiconductor chip has: a plurality of first transmitting pads electrically connected with a first transmitting circuit formed in the first semiconductor chip; and a plurality of first receiving pads electrically connected with a first receiving circuit formed in the first semiconductor chip, wherein the second semiconductor chip has: a plurality of second transmitting pads electrically connected with a second transmitting circuit formed in the second semiconductor chip; and a plurality of second receiving pads electrically connected with a second receiving circuit formed in the second semiconductor chip, wherein the plurality of transformers of the third semiconductor chip has: at least one or more first transformers used to transmit a signal from the first semiconductor chip to the second semiconductor chip; and at least one or more second transformers used to transmit a signal from the second semiconductor chip to the first semiconductor chip, wherein the primary coil of the one or more first transformers is electrically connected with the plurality of first transmitting pads of the first semiconductor chip, wherein the secondary coil of the one or more first transformers is electrically connected with the plurality of second receiving pads of the second semiconductor chip, wherein the primary coil of the one or more second transformers is electrically connected with the plurality of second transmitting pads of the second semiconductor chip, wherein the secondary coil of the one or more second transformers is electrically connected with the plurality of first receiving pads of the first semiconductor chip, wherein, in plan view, the one or more second transformers are arranged closer to the second semiconductor chip than the one or more first transformers, and wherein, in plan view, the plurality of second transmitting pads is arranged closer to the first semiconductor chip than the plurality of second receiving pads.
11 . The semiconductor device according to claim 10 , wherein, in plan view, the plurality of second transmitting pads and the plurality of second receiving pads are arranged along the second side of the second semiconductor chip.
12 . The semiconductor device according to claim 11 , wherein, in plan view, the plurality of first transmitting pads and the plurality of first receiving pads are arranged along the first side of the first semiconductor chip.
13 . The semiconductor device according to claim 12 , wherein, in plan view, the plurality of first receiving pads is arranged closer to the second semiconductor chip than the plurality of first transmitting pads.
14 . The semiconductor device according to claim 10 , wherein a number of the one or more first transformers is larger than a number of the one or more second transformers.
15 . The semiconductor device according to claim 10 , further comprising: a plurality of leads; and a plurality of wires, wherein the sealing body seals a portion of each of the plurality of leads and the plurality of wires.
16 . The semiconductor device according to claim 15 , wherein the third semiconductor chip has: a plurality of first pads electrically connected with the primary coil of the one or more first transformers; a plurality of second pads electrically connected with the secondary coil of the one or more first transformers; a plurality of third pads electrically connected with the primary coil of the one or more second transformers; and a plurality of fourth pads electrically connected with the secondary coil of the one or more second transformers, and wherein the plurality of wires includes: a plurality of first wires electrically connecting the plurality of first transmitting pads with the plurality of first pads, respectively; a plurality of second wires electrically connecting the plurality of second receiving pads with the plurality of second pads, respectively; a plurality of third wires electrically connecting the plurality of second transmitting pads with the plurality of third pads, respectively; and a plurality of fourth wires electrically connecting the plurality of first receiving pads with the plurality of fourth pads, respectively.
17 . The semiconductor device according to claim 16 , wherein the first semiconductor chip further has a plurality of fifth pads, wherein the second semiconductor chip further has a plurality of sixth pads, wherein the plurality of wires further includes: a plurality of fifth wires electrically connecting the plurality of fifth pads with a plurality of first leads of the plurality of leads, respectively; and a plurality of sixth wires electrically connecting the plurality of sixth pads with a plurality of second leads of the plurality of leads, respectively.
18 . The semiconductor device according to claim 10 , wherein the plurality of first transmitting pads is electrically connected with the primary coil of the one or more first transformers, respectively; and wherein the plurality of second receiving pads is electrically connected with the secondary coil of the one or more first transformers, respectively.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The disclosure of Japanese Patent Application No. 2022-202056 filed on Dec. 19, 2022, including the specification, drawings and abstract is incorporated herein by reference in its entirety. BACKGROUND The present disclosure relates to a semiconductor device, and can be suitably used, for example, for a semiconductor device incorporating a plurality of semiconductor chips. Here, there are disclosed techniques listed below. [Patent Document 1] PCT International Publication No. 2015-114758 A semiconductor device in the form of a semiconductor package can be manufactured by mounting a semiconductor chip on a die pad, by electrically connecting a pad electrode of the semiconductor chip with a lead via a wire, and by resin sealing them. Patent Document 1 discloses a technique in which two coils in a semiconductor chip are inductively coupled to each other, thereby transmitting an electric signal. SUMMARY In a semiconductor device in which a signal is transmitted between two of three semiconductor chips by using two coils, which are magnetically coupled to each other, provided in another one of the three semiconductor chips, it would be required to improve a performance thereof. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. A semiconductor device according to an embodiment, includes: a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; a second semiconductor chip mounted on the second chip mounting portion; a third semiconductor chip mounted on the first chip mounting portion and having a plurality of transformers; and a sealing body sealing the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first chip mounting portion and the second chip mounting portion. Here, each of the plurality of transformers has a primary coil and a secondary coil that are magnetically coupled to each other. Also, the first chip mounting portion and the second chip mounting portion are adjacent to each other in a first direction. Also, the first semiconductor chip and the third semiconductor chip are adjacent to each other in a second direction that is perpendicular to the first direction. Also, in plan view, the third semiconductor chip has: a third side facing a first side of the first semiconductor chip; and a fourth side facing a second side of the second semiconductor chip. Also, in plan view, the plurality of transformers is arranged along the fourth side of the third semiconductor chip. Also, the first semiconductor chip has: a plurality of first transmitting pads electrically connected with a first transmitting circuit formed in the first semiconductor chip; and a plurality of first receiving pads electrically connected with a first receiving circuit formed in the first semiconductor chip. Also, the second semiconductor chip has: a plurality of second transmitting pads electrically connected with a second transmitting circuit formed in the second semiconductor chip; and a plurality of second receiving pads electrically connected with a second receiving circuit formed in the second semiconductor chip. Also, the plurality of transformers of the third semiconductor chip has: at least one or more first transformers used to transmit a signal from the first semiconductor chip to the second semiconductor chip; and at least one or more second transformers used to transmit a signal from the second semiconductor chip to the first semiconductor chip. Also, the primary coil of the one of more first transformers is electrically connected with the plurality of first transmitting pads of the first semiconductor chip. Also, the secondary coil of the one of more first transformers is electrically connected with the plurality of second receiving pads of the second semiconductor chip. Also, the primary coil of the one of more second transformers is electrically connected with the plurality of second transmitting pads of the second semiconductor chip. Also, the secondary coil of the one of more second transformers is electrically connected with the plurality of first receiving pads of the first semiconductor chip. Also, in plan view, the one of more first transformers are arranged closer to the first semiconductor chip than the one of more second transformers. Further, in plan view, the plurality of first transmitting pads is arranged closer to the second semiconductor chip than the plurality of first receiving pads. According to one embodiment, the performance of the semiconductor device can be improved. In addition, it is possible to reduce the size of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an inverter circuit using a semiconductor device according to an embodiment. FIG. 2 is an upper surface view of the semiconductor device according to the embodimen