US-12628716-B2 - Semiconductor device

Abstract

A semiconductor device includes: a conductive substrate; a plurality of semiconductor chips each having a first main electrode on a bottom surface side and a second main electrode on a top surface side, the plural semiconductor chips being arranged to form a first column and a second column connected parallel to each other on the conductive substrate; and a control wiring substrate including an insulating layer, a plurality of top-surface conductive layers provided on a top surface of the insulating layer, and a plurality of bottom-surface conductive layers each having a narrower width than the insulating layer and provided on a bottom surface of the insulating layer, the bottom-surface conductive layers being arranged on the conductive substrate between the first column and the second column of the semiconductor chips.

Inventors

• Kensuke Matsuzawa
• Taisuke FUKUDA

Assignees

• FUJI ELECTRIC CO., LTD.

Dates

Publication Date

20260512

Application Date

20231026

Priority Date

20221117

Claims (4)

1. 1 . A semiconductor device comprising: a conductive substrate; a plurality of semiconductor chips each having a first main electrode on a bottom surface side and a second main electrode on a top surface side, the plural semiconductor chips being arranged to form a first column and a second column connected parallel to each other on the conductive substrate; and a control wiring substrate including an insulating layer, a plurality of top-surface conductive layers provided on a top surface of the insulating layer, and a plurality of bottom-surface conductive layers each having a narrower width than the insulating layer and provided on a bottom surface of the insulating layer, the bottom-surface conductive layers being arranged on the conductive substrate between the first column and the second column of the semiconductor chips.
2. 2 . The semiconductor device of claim 1 , further comprising a temperature detection chip on the control wiring substrate.
3. 3 . The semiconductor device of claim 1 , wherein the plural top-surface conductive layers extend parallel to each other and have wide regions alternately arranged.
4. 4 . The semiconductor device of claim 1 , wherein the plural top-surface conductive layers each have a terminal.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims benefit of priority under 35 USC 119 based on Japanese Patent Application No. 2022-184467 filed on Nov. 17, 2022, the entire contents of which are incorporated by reference herein. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device (a power semiconductor module) equipped with power semiconductor elements. 2. Description of the Related Art US 2021/0384111 A1 discloses a semiconductor package including a distribution element provided with a first transmission path for a first electrical signal between a first lead and a first bond pad of one or more semiconductor dies and a second transmission path for the first electrical signal between the first lead and a second bond pad of the one or more semiconductor dies, wherein the distribution element includes at least one integrally-formed circuit element that creates a difference in transmission characteristics between the first and second transmission paths. JP 2021-141220 A discloses a semiconductor device including a control wiring substrate arranged between a first column and a second column of a plurality of semiconductor elements connected in parallel to each other and including a gate wiring layer and a source wiring layer each extending parallel to the direction in which the first and second columns are arranged, a gate wiring member connecting one of gate electrodes of the semiconductor elements to the gate wiring layer, and a source wiring member connecting one of source electrodes of the semiconductor elements to the source wiring layer. JP 2019-71502 A discloses a semiconductor device including a printed substrate arranged at circumferential edges of a housing parts housing a stacked substrate in a case, the printed substrate being provided thereon with a terminal block holding a control terminal, wherein a gate electrode of a semiconductor chip and the printed substrate are electrically connected to each other via wires. The conventional power semiconductor modules, if the semiconductor chip is mounted on the circuit pattern of the insulated circuit substrate, and the semiconductor chip is electrically connected to a control wiring substrate provided as another member different from the insulated circuit substrate via lead frames and bonding wires, have a problem that a width of an insulating region of the control wiring substrate needs to be widely ensured in order to keep a creepage insulating distance between the wires provided in the control wiring substrate and the pattern layer on the insulated circuit substrate. SUMMARY OF THE INVENTION In view of the foregoing problems, the present invention provides a semiconductor device having a configuration capable of decreasing an area of a control wiring substrate to be provided. An aspect of the present invention inheres in a semiconductor device including: a conductive substrate; a plurality of semiconductor chips each having a first main electrode on a bottom surface side and a second main electrode on a top surface side, the plural semiconductor chips being arranged to form a first column and a second column connected parallel to each other on the conductive substrate; and a control wiring substrate including an insulating layer, a plurality of top-surface conductive layers provided on a top surface of the insulating layer, and a plurality of bottom-surface conductive layers each having a narrower width than the insulating layer and provided on a bottom surface of the insulating layer, the bottom-surface conductive layers being arranged on the conductive substrate between the first column and the second column of the semiconductor chips. The semiconductor device may further include a temperature detection chip on the control wiring substrate. In the semiconductor device, the plural top-surface conductive layers may extend parallel to each other and have wide regions alternately arranged. In the semiconductor device, the plural top-surface conductive layers each may have a terminal. It should be noted that the above summary of the invention does not list all the necessary features of the invention. Subcombinations of these feature groups can also be inventions. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view illustrating a semiconductor device according to a first embodiment; FIG. 2 is a plan view corresponding to FIG. 1; FIG. 3 is a perspective view omitting the illustration of a part of the semiconductor device according to the first embodiment; FIG. 4 is a plan view corresponding to FIG. 3: FIG. 5 is a side view corresponding to FIG. 3 and FIG. 4; FIG. 6 is an enlarged side view illustrating region A in FIG. 5; FIG. 7 is a perspective view omitting the illustration of a part of the semiconductor device according to the first embodiment; FIG. 8 is a plan view corresponding to FIG. 7; FIG. 9 is a perspective view illustrating a conductive member of the semiconducto