US-20260126328-A1 - THERMAL SENSOR USING INVERSION DIFFUSIVITY RESISTANCE

Abstract

A device including a first plurality of metal-oxide semiconductor field-effect transistors electrically connected in series. Each of the first plurality of metal-oxide semiconductor field-effect transistors includes a first gate structure, a first drain/source region on one side of the first gate structure, and a second drain/source region on another side of the first gate structure. The first gate structure of each of the first plurality of metal-oxide semiconductor field-effect transistors is configured to receive a bias voltage to bias on the first plurality of metal-oxide semiconductor field-effect transistors and provide a temperature dependent resistance through the first plurality of metal-oxide semiconductor field-effect transistors to measure temperatures.

Inventors

• Jaw-Juinn Horng
• Szu-Lin LIU
• Yung-Chow Peng
• Shenggao Li

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20260106

Claims (20)

1. 1 . A device, comprising: a first plurality of metal-oxide semiconductor field-effect transistors electrically connected in series, each of the first plurality of metal-oxide semiconductor field-effect transistors including: a first gate structure; a first drain/source region on one side of the first gate structure; and a second drain/source region on another side of the first gate structure, wherein the first gate structure of each of the first plurality of metal-oxide semiconductor field-effect transistors is configured to receive a bias voltage to bias on the first plurality of metal-oxide semiconductor field-effect transistors and provide a temperature dependent resistance through the first plurality of metal-oxide semiconductor field-effect transistors to measure temperatures.
2. 2 . The device of claim 1 , wherein the second drain/source region of one of the first plurality of metal-oxide semiconductor field-effect transistors is shared with the first drain/source region of an adjacent one of the first plurality of metal-oxide semiconductor field-effect transistors.
3. 3 . The device of claim 1 , wherein if each of the first plurality of metal-oxide semiconductor field-effect transistors is an n-type transistor, the first gate structure of each of the first plurality of metal-oxide semiconductor field-effect transistors is electrically connected to a positive voltage.
4. 4 . The device of claim 1 , wherein if each of the first plurality of metal-oxide semiconductor field-effect transistors is a p-type transistor, the first gate structure of each of the first plurality of metal-oxide semiconductor field-effect transistors is electrically connected to ground.
5. 5 . The device of claim 1 , wherein the first drain/source region of a first transistor in the first plurality of metal-oxide semiconductor field-effect transistors is electrically connected to a higher voltage and the second drain/source region of a last transistor in the first plurality of metal-oxide semiconductor field-effect transistors is electrically connected to a lower voltage.
6. 6 . The device of claim 1 , comprising: a second plurality of metal-oxide semiconductor field-effect transistors electrically connected in series, each of the second plurality of metal-oxide semiconductor field-effect transistors including: a second gate structure; a third drain/source region on one side of the second gate structure; and a fourth drain/source region on another side of the second gate structure, wherein the third drain/source region of a first transistor in the second plurality of metal-oxide semiconductor field-effect transistors is electrically connected to the first drain/source region of a first transistor in the first plurality of metal-oxide semiconductor field-effect transistors, and the fourth drain/source region of a last transistor in the second plurality of metal-oxide semiconductor field-effect transistors is electrically connected to the second drain/source region of a last transistor in the first plurality of metal-oxide semiconductor field-effect transistors.
7. 7 . The device of claim 6 , wherein the second gate structure of each of the second plurality of metal-oxide semiconductor field-effect transistors is electrically connected to a bias voltage configured to bias on each of the second plurality of metal-oxide semiconductor field-effect transistors.
8. 8 . The device of claim 6 , wherein the fourth drain/source region of one of the second plurality of metal-oxide semiconductor field-effect transistors is shared with the third drain/source region of an adjacent one of the second plurality of metal-oxide semiconductor field-effect transistors.
9. 9 . The device of claim 1 , comprising an active region, wherein the first gate structure of each of the first plurality of metal-oxide semiconductor field-effect transistors crosses the active region.
10. 10 . A device, comprising: a hot spot area; and an array of temperature sensing units arranged in rows and/or columns proximate the hot spot area and configured to measure a temperature of the hot spot area, wherein each of the temperature sensing units includes: an active region; and a plurality of gate structures that are spaced apart from one another and cross the active region.
11. 11 . The device of claim 10 , wherein the plurality of gate structures are configured to receive a bias voltage that biases on transistors that correspond to the plurality of gate structures to provide an inversion diffusivity resistance through the transistors.
12. 12 . The device of claim 10 , comprising a dummy pattern situated on at least one side of the array of temperature sensing units.
13. 13 . The device of claim 10 , wherein at least one of the rows or one of the columns includes multiple active regions that extend in a direction of the at least one of the rows or one of the columns.
14. 14 . The device of claim 10 , wherein at least one of the rows or one of the columns includes one active region that extends the full length of the at least one of the rows or one of the columns.
15. 15 . The device of claim 10 , wherein two or more of the temperature sensing units are used to determine a differential voltage to measure temperatures.
16. 16 . A method of measuring temperature, comprising: biasing on each transistor of a first plurality of metal-oxide semiconductor field-effect transistors that are connected in series by providing a first bias voltage to first gate structures situated across a first active region and spaced apart from one another; providing a first constant current to a first drain/source region at a first end of the first active region; providing a first reference voltage to a second drain/source region at a second end of the first active region; measuring a first voltage from the first drain/source region at the first end of the first active region to the second drain/source region at the second end of the first active region; determining a first resistance through the first plurality of metal-oxide semiconductor field-effect transistors; and determining a temperature using the first resistance.
17. 17 . The method of claim 16 , comprising: biasing on each transistor of a second plurality of metal-oxide semiconductor field-effect transistors that are connected in series by providing a second bias voltage to second gate structures situated across a second active region and spaced apart from one another; providing a second constant current to a third drain/source region at a first end of the second active region; providing a second reference voltage to a fourth drain/source region at a second end of the second active region; measuring a second voltage from the first drain/source region at the first end of the second active region to the second drain/source region at the second end of the second active region; determining a second resistance through the first plurality of metal-oxide semiconductor field-effect transistors.
18. 18 . The method of claim 17 , comprising: determining the temperature based on a difference between the first resistance and the second resistance.
19. 19 . The method of claim 16 , comprising: biasing on each of a second plurality of metal-oxide semiconductor field-effect transistors that are connected in series by providing the first bias voltage to second gate structures that are situated across a second active region and spaced apart from one another, wherein a third drain/source region at a first end of the second active region is connected to the first drain/source region, and a fourth drain/source region at a second end of the second active region is connected to the second drain/source region.
20. 20 . The method of claim 19 , wherein determining the first resistance through the first plurality of metal-oxide semiconductor field-effect transistors includes determining the first resistance through the first plurality of metal-oxide semiconductor field-effect transistors and the second plurality of metal-oxide semiconductor field-effect transistors.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application is a divisional of U.S. patent application Ser. No. 17/735,887, filed May 3, 2022, and titled: THERMAL SENSOR USING INVERSION DIFFUSIVITY RESISTANCE,” the entire disclosure of which is hereby incorporated by reference. BACKGROUND In thermal sensing, some devices utilize a P/N junction, such as a base-emitter junction in a bipolar junction transistor (BJT) or a P/N junction in a diode, to measure the temperature of a hot spot in the device. For example, constant current is passed through a base-emitter junction to produce a voltage between the base and the emitter of a BJT. This base-emitter voltage Vbe is a linear function of the absolute temperature and the overall forward voltage drop has a temperature coefficient of approximately 2 millivolts (mV) per degree C. (° C.). Metal-oxide semiconductor field-effect transistor (MOSFET) circuits sometimes include an N-well diffusion layer within the substrate to facilitate the use of a P/N junction thermal sensor. However, newer processes do not include N-well diffusion layers, such that it is difficult to form a P/N junction for thermal sensing. Also, although sub-threshold MOSFET operation can be used to perform thermal sensing, often, the performance of sub-threshold MOSFETs is not consistent. In addition, resistance temperature detectors (RTDs) can be used for thermal sensing. However, RTDs use metal for thermal sensing, where bottom layer metal is usually reserved for routing and upper layer metal is often far away from the hot spot being monitored. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. In addition, the drawings are illustrative as examples of embodiments of the disclosure and are not intended to be limiting. FIG. 1 is a diagram schematically illustrating a semiconductor device that includes at least one inversion diffusivity resistance/resistor (IDR) thermal sensor, in accordance with some embodiments. FIG. 2 is a diagram schematically illustrating an IDR unit that includes a plurality of MOSFETs connected in series to one another, in accordance with some embodiments. FIG. 3 is a diagram schematically illustrating an IDR layout of the IDR unit of FIG. 2, in accordance with some embodiments. FIG. 4 is a diagram schematically illustrating a cross-section of the IDR layout taken along the line A-A in FIG. 3, in accordance with some embodiments. FIG. 5 is a diagram schematically illustrating a graph of the error in measuring temperature using standard voltage threshold (SVT) MOSFET devices in an IDR unit, in accordance with some embodiments. FIG. 6 is a diagram schematically illustrating a graph of the error in measuring temperature using SVT MOSFET devices in an IDR unit and one-point calibration, in accordance with some embodiments. FIG. 7 is a diagram schematically illustrating a graph of the error in measuring temperature using low threshold voltage (LVT) MOSFET devices in an IDR unit and one-point calibration, in accordance with some embodiments. FIG. 8 is a diagram schematically illustrating a graph of the error in measuring temperature using ultra low threshold voltage (ULVT) MOSFET devices in an IDR unit and one-point calibration, in accordance with some embodiments. FIG. 9 is a block diagram schematically illustrating an example of a computer system configured to provide an integrated circuit (IC) device that includes at least one IDR thermal sensor, in accordance with some embodiments. FIG. 10 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith, in accordance with some embodiments. FIG. 11 is a diagram schematically illustrating a thermal sensor that includes an IDR unit array surrounded by a dummy pattern, in accordance with some embodiments. FIG. 12 is a diagram schematically illustrating a thermal sensor that includes an IDR unit array that includes three different IDR units that each have a different number of MOSFETs, in accordance with some embodiments. FIG. 13 is a diagram schematically illustrating a thermal sensor configured to measure the temperature of a hot spot area in a device, in accordance with some embodiments. FIG. 14 is a diagram schematically illustrating a thermal sensor that includes an IDR unit array that includes four different IDR units configured to measure the temperature of a hot spot area in a device, in accordance with some embodiments. FIG. 15 is a diagram schematically illustrating a first IDR unit that includes a plurality of MOSFETs connected in series to one another, in accordance with some embodiments. FIG. 16 is a diagram schematically illustrating a secon