US-20260126469-A1 - PROBE HEAD, PROBE CARD ASSEMBLY AND METHOD FOR MANUFACTURING PROBE HEAD

US20260126469A1US 20260126469 A1US20260126469 A1US 20260126469A1US-20260126469-A1

Abstract

A probe head for performing an electrical test on a device under test (DUT) includes an upper substrate including a plurality of upper through holes, a lower substrate assembly disposed under the upper substrate and including a plurality of lower through holes corresponding to the plurality of upper through holes respectively, a spacer connected between the upper substrate and the lower substrate assembly to maintain a gap between the upper substrate and the lower substrate assembly, a plurality of first probes extending through the plurality of upper through holes and the plurality of lower through holes respectively, an interconnect structure disposed on the lower substrate assembly and comprising a dielectric layer and a circuit layer, and a plurality of second probes disposed on the interconnect structure and electrically connected to one another through the circuit layer.

Inventors

Kuan Chun Chen
Guang-Sing HUANG
Shu An SHANG
Hsiou-Yu He
Kai-Yi Tang
Tsai-Ning LU

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241104

Claims (20)

1 . A probe head for performing an electrical test on a device under test (DUT), comprising: an upper substrate comprising a plurality of upper through holes; a lower substrate assembly disposed under the upper substrate and comprising a plurality of lower through holes corresponding to the plurality of upper through holes respectively; a spacer connected between the upper substrate and the lower substrate assembly to maintain a gap between the upper substrate and the lower substrate assembly; a plurality of first probes extending through the plurality of upper through holes and the plurality of lower through holes respectively; an interconnect structure disposed on the lower substrate assembly and comprising a dielectric layer and a circuit layer; and a plurality of second probes disposed on the interconnect structure and electrically connected to one another through the circuit layer.
2 . The probe head as claimed in claim 1 , wherein the lower substrate assembly further comprising an adhesive layer, and the interconnect structure is disposed over the adhesive layer on the lower substrate assembly.
3 . The probe head as claimed in claim 2 , wherein the plurality of first probes comprises a ground probe for contacting a ground pad of the DUT, and the adhesive layer is conductive and covers an inner surface of one of the plurality of lower through holes where the ground probe protrudes therefrom.
4 . The probe head as claimed in claim 1 , wherein the lower substrate assembly comprises a lower substrate comprising the plurality of lower through holes, and the interconnect structure is disposed on a lower surface of the lower substrate that faces the DUT.
5 . The probe head as claimed in claim 4 , wherein a dielectric constant of the dielectric layer is lower than a dielectric constant of the lower substrate.
6 . The probe head as claimed in claim 1 , wherein the lower substrate assembly comprises a lower substrate comprising the plurality of lower through holes and a plurality of interconnect through holes, the dielectric layer covers inner surfaces of the plurality of interconnect through holes and extends over an upper surface of the lower substrate that faces the upper substrate, and the circuit layer fills the plurality of interconnect through holes and extends over the upper surface of the lower substrate.
7 . The probe head as claimed in claim 6 , wherein the lower substrate assembly further comprising an adhesive layer covering inner surfaces of the plurality of interconnect through holes and the upper surface of the lower substrate assembly, and the interconnect structure is disposed over the adhesive layer on the upper surface of the lower substrate assembly.
8 . The probe head as claimed in claim 7 , wherein the plurality of first probes comprises a ground probe, and the adhesive layer is conductive and connected to the ground probe.
9 . The probe head as claimed in claim 1 , wherein the lower substrate assembly further comprises a lower substrate comprising the plurality of lower through holes and an auxiliary substrate disposed under and spaced apart from the lower substrate, wherein the auxiliary substrate comprises a plurality of auxiliary through holes, and the plurality of first probes extending through the plurality of auxiliary through holes respectively.
10 . The probe head as claimed in claim 9 , wherein the interconnect structure is bonded to a lower surface of the auxiliary substrate facing the DUT through an adhesive layer.
11 . The probe head as claimed in claim 9 , wherein the auxiliary substrate further comprises a plurality of interconnect through holes, the dielectric layer covers inner surfaces of the plurality of interconnect through holes and extends over an upper surface of the auxiliary substrate that faces the lower substrate, and the circuit layer fills the plurality of interconnect through holes and extends over the upper surface of the lower substrate.
12 . A probe card assembly comprising: a circuit board; a space transformer disposed over the circuit board; and a probe head disposed on the circuit board and comprising: an upper substrate; a lower substrate assembly disposed in parallel to the upper substrate; a spacer connected between the upper substrate and the lower substrate assembly; a plurality of first probes extending through the upper substrate and the lower substrate assembly; an interconnect structure disposed on the lower substrate assembly; and a plurality of second probes disposed on the interconnect structure and electrically connected to one another through the interconnect structure.
13 . The probe card assembly as claimed in claim 12 , further comprising a jig mounted on the circuit board and configured to connect the probe head to the circuit board.
14 . The probe card assembly as claimed in claim 13 , wherein the spacer is mounted on the jig for connecting the probe head to the circuit board.
15 . The probe card assembly as claimed in claim 12 , wherein the lower substrate assembly further comprising an adhesive layer, and the interconnect structure is disposed on the lower substrate assembly through the adhesive layer, and the adhesive layer is conductive and coupled to a ground probe of the plurality of first probes.
16 . A method for manufacturing a probe head, comprising: providing a lower substrate assembly comprising a plurality of lower through holes; forming an adhesive layer on a surface of the lower substrate assembly; forming an interconnect structure on the adhesive layer; providing a plurality of loopback probes on the interconnect structure, wherein the plurality of loopback probes electrically connected to one another through the interconnect structure; mounting an upper substrate over the lower substrate assembly through a spacer, wherein the upper substrate having a plurality of upper through holes; and providing a plurality of probes extending through the plurality of upper through holes and the plurality of lower through holes respectively.
17 . The method for manufacturing the probe head as claimed in claim 16 , wherein the plurality of lower through holes comprises a ground through hole, the plurality of probes comprises a ground probe extending through the ground through hole, the adhesive layer further covers an inner surface of the ground through hole and coupled to the ground probe.
18 . The method for manufacturing the probe head as claimed in claim 16 , wherein the lower substrate assembly further comprises a plurality of interconnect through holes, and forming the interconnect structure further comprises: forming a dielectric layer covering inner surfaces of the plurality of interconnect through holes and extends over an upper surface of the lower substrate assembly; and forming a circuit layer on the dielectric layer, wherein the circuit layer fills the plurality of interconnect through holes and extends over the upper surface of the lower substrate assembly.
19 . The method for manufacturing the probe head as claimed in claim 16 , wherein providing the lower substrate assembly further comprises: providing a lower substrate comprising the plurality of lower through holes; providing an auxiliary substrate comprising a plurality of auxiliary through holes, wherein the auxiliary substrate is disposed under the lower substrate, and the plurality of probes extend through the plurality of auxiliary through holes respectively.
20 . The method for manufacturing the probe head as claimed in claim 19 , wherein the adhesive layer is formed on a lower surface of the auxiliary substrate where the interconnect structure is disposed.

Description

BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer. The dies of the wafer may be processed and packaged at the wafer level, and various technologies have been developed for wafer level packaging. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross sectional view of a probe head according to some embodiments of the present disclosure. FIG. 2 to FIG. 8 illustrate cross sectional views of intermediate stages in the manufacturing of a probe card assembly according to some embodiments of the present disclosure. FIG. 9 illustrates a partial bottom view of a lower substrate assembly of a probe head according to some embodiments of the present disclosure. FIG. 10 illustrates a partial bottom view of a lower substrate assembly of a probe head according to other embodiments of the present disclosure. FIG. 11 illustrates a cross sectional view of a probe card assembly during testing according to some embodiments of the present disclosure. FIG. 12 to FIG. 17 illustrate cross sectional views of intermediate stages in the manufacturing of a probe card assembly according to some embodiments of the present disclosure. FIG. 18 illustrates a cross sectional view of a probe card assembly according to some embodiments of the present disclosure. FIG. 19 to FIG. 23 illustrate cross sectional views of intermediate stages in the manufacturing of a probe card assembly according to some embodiments of the present disclosure. FIG. 24 illustrates a cross sectional view of a probe card assembly according to some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A probe head, probe card having the probe head and a method for manufacturing the probe head are provided for performing an electrical test on a device under test (DUT) (e.g., DUT 20 shown in FIG. 8). The device under test may be a semiconductor wafer in accordance with some embodiments of the disclosure. In general, semiconductor fabrication involves numerous steps including photolithography, material deposition, and etching to form a plurality of individual semiconductor devices or integrated circuit chips (dies) on a single semiconductor wafer. Some of the individual chips formed on the wafer, however, may have defects due to variances and problems that may arise during the intricate semiconductor fabrication process. Prior to wafer dicing wherein the individual integrated circuit chips (dies) are separated from the semiconductor wafer, electrical performance and reliability tests are performed on a plurality of chips simultaneously