US-20260126481-A1 - SEMICONDUCTOR DEVICE INCLUDING BONDING PADS AND METHOD FOR MEASURING CONTACT RESISTANCE OF BONDING PADS

US20260126481A1US 20260126481 A1US20260126481 A1US 20260126481A1US-20260126481-A1

Abstract

A semiconductor device including a first test pattern in which the first upper test pad, first upper test contacts, and first upper conductive layers connecting the first upper test contacts are sequentially connected, a second test pattern in which the second lower test pad, second lower test contacts, and second lower conductive layers connecting the second lower test contacts are sequentially connected, and a third test pattern including a third upper conductive layer, a third lower conductive layer, a third upper test contact, a third upper test pad, a third lower test pad, and a third lower test contact.

Inventors

Heon Yong Chang

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260507
Application Date: 20250307
Priority Date: 20241101

Claims (18)

1 . A semiconductor device comprising: a memory chip including a cell bonding pad disposed in a cell region, and upper test pads disposed outside the cell region, the upper test pads including first, second, and third upper test pads; a circuit chip including a peripheral bonding pad disposed in the cell region, and lower test pads disposed outside the cell region, the lower cell pads including first, second, and third lower test pads; and test patterns disposed outside the cell region, each of which includes at least a part of the upper test pads or the lower test pads, wherein the peripheral bonding pad is bonded to the cell bonding pad, and wherein the test patterns comprise: a first test pattern in which the first upper test pad, first upper test contacts connected to each of the first upper test pads, and first upper conductive layers connecting the first upper test contacts connected to different first upper test pads are sequentially connected; a second test pattern in which the second lower test pad, second lower test contacts connected to each of the second lower test pads, and second lower conductive layers connecting the second lower test contacts connected to different second lower test pads are sequentially connected; and a third test pattern including a third upper conductive layer, a third lower conductive layer, a third upper test contact connected to the third upper conductive layer, a third upper test pad connected to the third upper test contact, a third lower test pad connected to the third upper test pad, and a third lower test contact connected to the third lower test pad and the third lower conductive layer.
2 . The semiconductor device of claim 1 , further comprising a pair of probing pads each connected to the first test pattern, the second test pattern, or the third test pattern, wherein the probing pads include a first probing input pad and a first probing output pad connected to the first test pattern at different locations, a second probing input pad and a second probing output pad connected to the second test pattern at different locations, and a third probing input pad and a third probing output pad connected to the third test pattern at different locations, wherein voltages of different magnitudes are applied to each of the first probing input pad and the first probing output pad, the second probing input pad and the second probing output pad, or the third probing input pad and the third probing output pad, wherein a resistance between the first probing input pad and the first probing output pad, the second probing input pad and the second probing output pad, or the third probing input pad and the third probing output pad is measured based on a current value flowing between the first probing input pad and the first probing output pad, the second probing input pad and the second probing output pad, or the third probing input pad and the third probing output pad.
3 . The semiconductor device of claim 2 , wherein voltages of different magnitude are applied to the first probing input pad and the first probing output pad connected to the first test pattern, and a first resistance between the first upper test pad and the first upper test contact is measured based on a current value flowing between the first probing input pad and the first probing output pad, wherein voltages of different magnitude are applied to the second probing input pad and the second probing output pad connected to the second test pattern, and a second resistance between the second lower test pad and the second lower test contact is measured based on a current value flowing between the second probing input pad and the second probing output pad, wherein voltages of different magnitude are applied to the third probing input pad and third probing output pad connected to the third test pattern, and a third resistance between the third upper test contact and the third lower test contact is measured based on a current value flowing between the third probing input pad and the third probing output pad, and wherein a contact resistance between the cell bonding pad and the peripheral bonding pad is measured by subtracting the first resistance and the second resistance from the third resistance.
4 . The semiconductor device of claim 1 , wherein the first test pattern further includes a first lower test pad bonded to each of the first upper test pads.
5 . The semiconductor device of claim 1 , wherein the second test pattern further includes a second upper test pad bonded to each of the second lower test pads.
6 . The semiconductor device of claim 1 , wherein the third upper test pad included in the third test pattern overlaps with two or more of the third lower test pads.
7 . The semiconductor device of claim 6 , wherein voltages of different magnitude are applied to the second probing input pad and the second probing output pad connected to the second test pattern, and a second resistance between the second lower test pad and the second lower test contact is measured based on a current value flowing between the second probing input pad and the second probing output pad; wherein voltages of different magnitude are applied to the third probing input pad and the third probing output pad connected to the third test pattern, and a fourth resistance between the third upper test pad and the third lower test contact is measured based on a current value flowing between the third probing input pad and the third probing output pad; and wherein a contact resistance between the cell bonding pad and the peripheral bonding pad is measured by subtracting the second resistance from the fourth resistance.
8 . The semiconductor device of claim 1 , wherein the first to third upper test pads are disposed on the same layer as the cell bonding pads.
9 . The semiconductor device of claim 1 , wherein the memory chip further includes a peripheral region around the cell region, and wherein the first test pattern, the second test pattern and third test pattern are disposed in the peripheral region.
10 . The semiconductor device of claim 1 , wherein the memory chip further includes a chip region including the cell region and a peripheral region surrounding the cell region, and wherein the first test pattern, the second test pattern, and the third test pattern are disposed in a scribe lane region continuous with the chip region.
11 . A semiconductor device comprising: a memory chip including cell bonding pads disposed in a cell region, and upper test pads disposed outside the cell region; a circuit chip including peripheral bonding pads disposed in the cell region and bonded to the cell bonding pads, and lower test pads disposed outside the cell region; and test patterns disposed outside the cell region and including at least a part of the upper test pads or the lower test pads, wherein at least one of the test patterns includes a part of the upper test pads and a part of the lower test pads, wherein each of the part of the upper test pads is bonded to two of the part of the lower test pads, and each of the part of the lower test pads is bonded to two of the part of the upper test pads.
12 . The semiconductor device of claim 11 , further comprising a pair of probing pads connected to at least one of the test patterns, wherein the probing pads include a probing input pad and a probing output pad connected to at least one of the test patterns at different locations, wherein voltages of different magnitude are applied to the probing input pad and the probing output pad, and a resistance between the probing input pad and the probing output pad is measured based on a current value flowing between the probing input pad and the probing output pad.
13 . The semiconductor device of claim 12 , wherein voltages of different magnitudes are applied to the probing input pad and the probing output pad connected to at least one of the test patterns, and a contact resistance between the upper test pad and the lower test pad is measured by measuring a resistance between the probing input pad and the probing output pad based on a current value flowing between the probing input pad and the probing output pad.
14 . The semiconductor device of claim 11 , wherein the memory chip further includes a peripheral region around the cell region, and at least one test pattern is disposed in the peripheral region.
15 . A method of measuring contact resistance for determining bonding strength between a cell bonding pad and a peripheral bonding pad bonded to each other using at least a part of upper test pads including a first upper test pad, a second upper test pad, and a third upper test pad, or lower test pads including a first lower test pad, a second lower test pad, and a third lower test pad comprising: measuring a first resistance between the first upper test pad and a first upper test contact connected to the first upper test pad; measuring a second resistance between the second lower test pad and a second lower test contact connected to the second lower test pad; measuring a third resistance between a third upper test contact and the third lower test contact in a test pattern in which the third upper test contact, the third upper test pad, the third lower test pad, and the third lower test contact are sequentially connected; and measuring contact resistance between the cell bonding pad and the peripheral bonding pad by subtracting the first and second resistances from the third resistance, and evaluating the bonding strength between the cell bonding pad and the peripheral bonding pad based on the contact resistance.
16 . The method of claim 15 , wherein measuring a first resistance comprises: connecting a pair of probing pads to a first test pattern in which the first upper test pad, the first upper test contact, and a first upper conductive layer connecting the first upper test contacts, each of which is connected to a different first upper test pad, are sequentially connected; and applying different voltages to each of the pair of probing pads.
17 . The method of claim 15 , wherein measuring a second resistance comprises: connecting a pair of probing pads to a second test pattern in which the second lower test pad, the second lower test contact, and a second lower conductive layer connecting the second lower test contacts, each of which is connected to a different second lower test pad, are sequentially connected; and applying different voltages to each of the pair of probing pads.
18 . The method of claim 15 , wherein, in measuring the third resistance, one third upper test pad overlaps with at least two third lower test pads.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority under 35 U.S.C. 119(a) to Korean patent application number 10-2024-0153570 filed on Nov. 1, 2024, which is incorporated herein by reference in its entirety. TECHNICAL FIELD The embodiments of the present disclosure relate generally to semiconductor technology and, more particularly to a semiconductor device including bonding pads and a method for measuring contact resistance of bonding pads. BACKGROUND A memory device is an important component in an electronics industry owing to their characteristics such as miniaturization, multi-functionality, and/or low manufacturing cost. As the electronics industry develops, memory devices are gradually becoming more highly integrated. In order to achieve high integration of the memory device, a technology has been proposed that forms the various semiconductor device components and circuits in two separate wafers and then bonding the two wafers together in a vertical direction by using wafer bonding technology. This technology is rather fairly new and further improvements are needed. SUMMARY Various embodiments of the present disclosure provide a semiconductor device including bonding pads and method for measuring contact resistance of bonding pads capable of accurately measuring resistance between bonding pads. Various embodiments of the present disclosure provide a semiconductor device including a memory chip including a cell bonding pad disposed in a cell region, and upper test pads disposed outside the cell region and including first, second, and third upper test pad; a circuit chip including a peripheral bonding pad disposed in the cell region and bonded to the cell bonding pad, and lower test pads disposed outside the cell region and including first, second, and third lower test pad; and test patterns disposed outside the cell region, each of which includes at least a part of the upper test pads and the lower test pads. In this case, the test patterns may include a first test pattern in which the first upper test pad, first upper test contacts connected to each of the first upper test pads, and first upper conductive layers connecting the first upper test contacts connected to different first upper test pads are sequentially connected; a second test pattern in which the second lower test pad, second lower test contacts connected to each of the second lower test pads, and second lower conductive layers connecting the second lower test contacts connected to different second lower test pads are sequentially connected; and a third test pattern including a third upper conductive layer, a third lower conductive layer, and a third upper test contact connecting between the third upper conductive layer and the lower conductive layer, a third upper test pad, a third lower test pad, and a third lower test contact. Various embodiments of the present disclosure may provide a semiconductor device including a memory chip including cell bonding pads disposed in a cell region, and upper test pads disposed outside the cell region; a circuit chip including peripheral bonding pads disposed in the cell region and bonded to the cell bonding pads, and lower test pads disposed outside the cell region; and test patterns disposed outside the cell region and including at least a part of the upper test pads and the lower test pads. At least one of the test patterns may include a part of the upper test pads and a part of the lower test pads. Each of the part of the test pads may be bonded to two of the part of the lower test pads, and each of the part of the lower test pads may be bonded to two of the part of the test pads. Various embodiments of the present disclosure may provide a method of measuring contact resistance for determining bonding strength between a cell bonding pad and a peripheral bonding pad bonded to each other using at least a part of upper test pads including a first upper test pad, a second upper test pad, and a third upper test pad, and lower test pads including a first lower test pad, a second lower test pad, and a third lower test pad. The method may include measuring a first resistance between the first upper test pad and a first upper test contact connected to the first upper test pad; measuring a second resistance between the second lower test pad and a second lower test contact connected to the second lower test pad; measuring a third resistance between a third upper test contact and the third lower test contact in a test pattern in which the third upper test contact, the third upper test pad, the third lower test pad, and the third lower test contact are sequentially connected; and measuring contact resistance between the cell bonding pad and the peripheral bonding pad by subtracting the first and second resistances from the third resistance, and evaluating the bonding strength between the cell bonding pad and the peripheral bonding pad based on the contact resistance. According to som