US-20260126484-A1 - METHODS AND APPARATUS TO ESTIMATE ANALOG TO DIGITAL CONVERTER (ADC) ERROR

Abstract

An example apparatus includes programmable circuitry configured to: determine a first output voltage from a first analog to digital converter (ADC) responsive to the first ADC and a second ADC both receiving a first input voltage; determine a first output voltage from a second ADC responsive to the first ADC and a second ADC both receiving the first input voltage; determine a second output voltage from the first ADC responsive to the first ADC receiving a second input voltage and the second ADC receiving the first input voltage; and determine an error value for the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC.

Inventors

• Nithin GOPINATH
• Sai Aditya Nurani
• Viswanathan Nagarajan
• Himanshu Varshney
• Mishab I
• Mujammil Patel

Assignees

• TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date

20260507

Application Date

20260105

Claims (20)

1. 1 . A method, comprising: providing a first dither signal, in addition to an input voltage, to both a first analog-to-digital converter (ADC) and a second ADC; determining a first output signal from the first ADC and a first output signal from the second ADC, responsive to providing the first dither signal, in addition to the input voltage, to both the first ADC and the second ADC; providing a second dither signal, in addition to the input voltage, to the first ADC, and the first dither signal, in addition to the input voltage, to the second ADC, wherein the second dither signal is different from the first dither signal; determining a second output signal from the first ADC, responsive to providing the second dither signal, in addition to the input voltage, to the first ADC and the first dither signal, in addition to, the input voltage, to the second ADC; and determining an error value based on the first output signal from the first ADC, the first output signal from the second ADC, and the second output signal from the first ADC.
2. 2 . The method of claim 1 , wherein the second dither signal differs from the first dither signal by a predetermined amount.
3. 3 . The method of claim 2 , wherein the predetermined amount represents one-half of a stage 1 least significant bit (Stg1_LSB/2) of the first ADC.
4. 4 . The method of claim 1 , further comprising: adjusting a scaling factor for the first ADC based on the error value.
5. 5 . The method of claim 4 , wherein the first ADC comprises a set of comparator circuits and delay to digital circuitry, and wherein adjusting the scaling factor comprises modifying an interpolation coefficient of at least one comparator circuit of the set of comparator circuits.
6. 6 . The method of claim 1 , wherein determining the error value comprises determining the error value based on a set of equations.
7. 7 . The method of claim 6 , wherein the set of equations comprises a first equation associated with a difference between the first output signal from the first ADC and the first output signal from the second ADC and a second equation associated with a difference between the second output signal from the first ADC and the first output signal from the second ADC.
8. 8 . The method of claim 1 , wherein the providing of the first dither signal to the first ADC and the second ADC, determining the first output signal from the first ADC and the first output signal from the second ADC, providing the second dither signal to the first ADC and the first dither signal to the second ADC, and determining the second output signal from the first ADC are performed iteratively for a threshold number of iterations, prior to determining the error value.
9. 9 . The method of claim 1 , the error value includes one or more of: an offset error value or a gain error value.
10. 10 . The method of claim 1 , wherein the input voltage is provided by a voltage source.
11. 11 . A system, comprising: a first analog-to-digital converter (ADC); and a second ADC; and controller circuitry, wherein the controller circuitry is configurable to: provide a first dither signal, in addition to an input voltage, to both the first ADC and the second ADC; determine a first output signal from the first ADC and a first output signal from the second ADC, responsive to providing the first dither signal, in addition to the input voltage, to both the first ADC and the second ADC; provide a second dither signal, in addition to the input voltage, to the first ADC, and the first dither signal, in addition to the input voltage, to the second ADC, wherein the second dither signal is different from the first dither signal; determine a second output signal from the first ADC, responsive to providing the second dither signal, in addition to the input voltage, to the first ADC and the first dither signal, in addition to, the input voltage, to the second ADC; and determine an error value based on the first output signal from the first ADC, the first output signal from the second ADC, and the second output signal from the first ADC.
12. 12 . The system of claim 11 , wherein the second dither signal differs from the first dither signal by a predetermined amount.
13. 13 . The system of claim 12 , wherein the predetermined amount represents one-half of a stage 1 least significant bit (Stg1_LSB/2) of the first ADC.
14. 14 . The system of claim 11 , wherein the controller circuitry is further configurable to: adjust a scaling factor for the first ADC based on the error value.
15. 15 . The system of claim 14 , wherein the first ADC comprises a set of comparator circuits and delay to digital circuitry, and wherein to adjust the scaling factor, the controller circuitry is configurable to modify an interpolation coefficient of at least one comparator circuit of the set of comparator circuits.
16. 16 . The system of claim 11 , wherein to determine the error value, the controller circuitry is configurable to determine the error value based on a set of equations.
17. 17 . The system of claim 16 , wherein the set of equations comprises a first equation associated with a difference between the first output signal from the first ADC and the first output signal from the second ADC and a second equation associated with a difference between the second output signal from the first ADC and the first output signal from the second ADC.
18. 18 . The system of claim 11 , wherein prior to determining the error value, the controller circuitry is configurable to provide the first dither signal to the first ADC and the second ADC, determine the first output signal from the first ADC and the first output signal from the second ADC, provide the second dither signal to the first ADC and the first dither signal to the second ADC, and determine the second output signal from the first ADC iteratively for a threshold number of iterations.
19. 19 . The system of claim 11 , the error value includes one or more of: an offset error value or a gain error value.
20. 20 . The system of claim 11 , wherein the input voltage is provided by a voltage source.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/217,292, filed Jun. 30, 2023, which is hereby incorporated herein by reference in its entirety. TECHNICAL FIELD This description relates generally to analog to digital converters and, more particularly, to methods and apparatus to estimate ADC error. BACKGROUND Information may be represented in electronic devices as either a digital or analog signal. In many applications, information requires conversion from an analog signal to a digital signal. For example, an analog voltage may be received over a transmission medium. The analog voltage may be transformed into a digital value. The digital voltage may be stored in a memory circuit, interpreted by processor circuitry, etc. ADC circuits perform the conversion of analog values to digital voltages and are used in a variety of computing devices. In some examples, the analog to digital conversion can degrade the quality of the signal, causing information to be lost or distorted. Therefore, signal integrity may be used as a performance metric of an ADC circuit. SUMMARY For methods and apparatus to correct for ADC error, an example apparatus includes programmable circuitry configured to: determine a first output voltage from a first analog to digital converter (ADC) responsive to the first ADC and a second ADC both receiving a first input voltage; determine a first output voltage from a second ADC responsive to the first ADC and a second ADC both receiving the first input voltage; determine a second output voltage from the first ADC responsive to the first ADC receiving a second input voltage and the second ADC receiving the first input voltage; and determine an error value for the first ADC based on: (a) a difference between the first output voltage from the first ADC and the first output voltage from the second ADC, and (b) a difference between the first output voltage from the first ADC and the second output voltage from the first ADC. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an example implementation of a compute environment. FIG. 2 is a block diagram of an example implementation of the ADC circuitry of FIG. 1. FIG. 3A is a block diagram showing an example implementation of the internal ADC circuits of FIG. 2. FIG. 3B is a graph illustrating an example offset error of a comparator of the ADC circuit of FIG. 3A. FIG. 4A is a graph illustrating an example offset error of both internal ADC circuits of FIG. 2 when no dither value is applied. FIG. 4B is a graph illustrating an example offset error of both internal ADC circuits of FIG. 2 when a first dither value is applied. FIG. 5 is a graph illustrating an example offset error and an example gain error of an internal ADC circuit of FIG. 2. FIG. 6 is a table describing an example implementation of dither signals provided to the internal ADC circuits of FIG. 2. FIG. 7 is a flowchart representative of example machine readable instructions and/or example operations that may be executed, instantiated, and/or performed to implement the ADC circuitry 104. FIG. 8 is a first flowchart representative of example machine readable instructions and/or example operations that may be executed, instantiated, and/or performed using an example programmable circuitry to adjust for offset and/or gain error as described in FIG. 7. FIG. 9 is a second flowchart representative of example machine readable instructions and/or example operations that may be executed, instantiated, and/or performed using an example programmable circuitry to adjust for offset and/or gain error as described in FIG. 7. FIG. 10 is a third flowchart representative of example machine readable instructions and/or example operations that may be executed, instantiated, and/or performed using an example programmable circuitry to adjust for offset and/or gain error as described in FIG. 7. FIG. 11 is a graph describing an example performance of the ADC circuitry of FIG. 2 when subjected to offset error. FIG. 12 is a graph describing an example performance of the ADC circuitry of FIG. 2 when subjected to gain error. FIG. 13 is a block diagram of an example processing platform including programmable circuitry structured to execute, instantiate, and/or perform the example machine readable instructions and/or perform the example operations of FIGS. 7-10 to implement the controller circuitry 108 of FIG. 2. The same reference numbers or other reference designators are used in the drawings to designate the same or similar (functionally and/or structurally) features. DETAILED DESCRIPTION The drawings are not necessarily to scale. Generally, the same reference numbers in the drawing(s) and this description refer to the same or like parts. Although the drawings show regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended and/or irreg