US-20260126494-A1 - DISTRIBUTED COULOMB COUNTER

Abstract

In an example, a battery management system may include a host microcontroller, which may be operated in accordance with a first clock signal; and a first analog front end (AFE) circuit. The first AFE circuit may be operated in accordance with a second clock signal that may be unsynchronized with the first clock signal. The first AFE circuit may also include first digital circuitry to (1) accumulate a first value corresponding to a number of ADC sample cycles of the first ADC, and to (2) accumulate a second value corresponding to the digital output representative of the first battery current for the ADC sample cycles accumulated in the first value. The first AFE circuit may transfer a representation of the first value and a representation of the second value to the host microcontroller in response to a request from the host microcontroller.

Inventors

• Yijing LIN
• Yiwei BAI
• Yulei Nie

Assignees

• Analog Devices International Unlimited Company

Dates

Publication Date

20260507

Application Date

20250926

Priority Date

20211210

Claims (20)

1. 1 . (canceled)
2. 2 . An electrochemical cell management system comprising: a first analog front end (AFE) circuit, the first AFE circuit comprising: a first analog-to-digital converter (ADC), including first ADC inputs configured to receive an indication of a first current associated with one or more cells in an electrochemical cell system, and providing a digital output representative of the first current; and first digital circuitry to (1) accumulate a first value corresponding to a number of ADC sample cycles of the first ADC, and to (2) accumulate a second value corresponding to the digital output representative of the first current for the ADC sample cycles accumulated in the first value; and an interface, wherein the first AFE circuit is configured to transfer a representation of the first value and a representation of the second value to a host microcontroller via the interface.
3. 3 . The electrochemical cell management system of claim 2 , wherein: the first AFE circuit comprises: a first gain amplifier, including first gain amplifier inputs configured to receive a signal corresponding to the first current, and first gain amplifier outputs to provide the signal representative of the first current to the first ADC.
4. 4 . The electrochemical cell management system of claim 3 , wherein: the interface is configured to transfer a representation of a gain setting of the first gain amplifier to the host microcontroller.
5. 5 . The electrochemical cell management system of claim 4 , wherein: the interface is configured for dividing the output of the first ADC by the gain setting prior to accumulating the second value.
6. 6 . The electrochemical cell management system of claim 2 , wherein: the host microcontroller is operated in accordance with a first clock signal; and the first AFE circuit is operated in accordance with a second clock signal that is unsynchronized with the first clock signal.
7. 7 . The electrochemical cell management system of claim 6 , further comprising: the host microcontroller.
8. 8 . The electrochemical cell management system of claim 7 , wherein the host microcontroller is configured to calculate a representation of a value of charge transfer corresponding to the first current, wherein the representation of the value of charge transfer is calculated at least in part based on the representation of the first value and the representation of the second value.
9. 9 . The electrochemical cell management system of claim 8 , wherein the host microcontroller is configured to calculate the representation of the value of charge transfer by (1) calculating a representation of an average value of the first current by dividing the representation of the second value by the representation of the first value, and (2) multiplying the representation of the average value of the first current by a time value corresponding to a period over which the first value and the second value were accumulated.
10. 10 . The electrochemical cell management system of claim 9 , wherein: a sampling timing of the first ADC is substantially periodic.
11. 11 . The electrochemical cell management system of claim 9 , wherein: the time value corresponding to a period over which the first value and the second value were accumulated is determined at the host microcontroller.
12. 12 . The electrochemical cell management system of claim 11 , wherein the first AFE includes a first holding register and a second holding register and is configured such that in response to a “snapshot” command from the host microcontroller, the first AFE (1) stores the first value in the first holding register and resets the first value, and (2) stores the second value in the second holding register and resets the second value.
13. 13 . The electrochemical cell management system of claim 12 , wherein the AFE is configured to start accumulating the first value following the reset of the first value and start accumulating the second value following the reset of the second value.
14. 14 . The electrochemical cell management system of claim 13 , wherein: the time value corresponding to a period over which the first value and the second value were accumulated is determined at the host microcontroller by determining a time value between adjacent “snapshot” commands sent from the host microcontroller to the first AFE circuit.
15. 15 . The electrochemical cell management system of claim 2 , comprising: a second AFE circuit, the second AFE circuit comprising: a second analog-to-digital converter (ADC), including second ADC inputs configured to receive an indication of a second current associated with one or more cells in the electrochemical cell system, and providing a digital output representative of the second current; and second digital circuitry to (1) accumulate a third value corresponding to a number of ADC sample cycles of the second ADC, and to (2) accumulate a fourth value corresponding to the digital output representative of the second current for the ADC sample cycles accumulated in the third value; and wherein the second AFE circuit is configured to transfer a representation of the third value and a representation of the fourth value to the host microcontroller.
16. 16 . The electrochemical cell management system of claim 15 , wherein: the host microcontroller is operated in accordance with a first clock signal; the first AFE circuit is operated in accordance with a second clock signal that is unsynchronized with the first clock signal; and the second AFE circuit is operated in accordance with a third clock signal that is unsynchronized with the first clock signal.
17. 17 . A method of operating an electrochemical cell management system, the method comprising: converting, using an analog-to-digital converter (ADC) included in an analog front end (AFE) circuit, an analog signal representation of a first current corresponding to one or more cells in an electrochemical cell system to a digital signal representation of the first current; accumulating, at the AFE circuit, (1) a first value corresponding to a number of ADC sample cycles, and (2) a second value corresponding to an accumulation of the digital signal representation of the first current for the ADC sample cycles accumulated in the first value; and transferring, from the AFE circuit to a host microcontroller, the first value and the second value.
18. 18 . The method of claim 17 , comprising: calculating, at the host microcontroller, a value representative of an accumulated charge transfer from the electrochemical cell based upon the first value and the second value.
19. 19 . The method of claim 18 , comprising: starting, at the host microcontroller, a timer at a time corresponding to when the first value and the second value began accumulation; stopping, at the host microcontroller, the timer at a time corresponding to when the first value and the second value stopped accumulation; receiving, at the host microcontroller from the AFE circuit, an indication of the first value and an indication of the second value; and calculating, at the host microcontroller, the value representative of charge transfer based upon the indication of the first value, the indication of the second value, and a time value determined by the timer.
20. 20 . An analog front end (AFE) circuit for use in a charge transfer measurement system, the AFE circuit comprising: an analog-to-digital converter (ADC), including ADC inputs configured to receive an indication of a current of interest, and providing a digital output representative of the current of interest; and digital circuitry to (1) accumulate a first value corresponding to a number of ADC sample cycles of the ADC, and to (2) accumulate a second value corresponding to the digital output representative of the current of interest for the ADC sample cycles accumulated in the first value; and a microcontroller interface, wherein the AFE circuit is configured to transfer a representation of the first value and a representation of the second value to a microcontroller, wherein the transfer occurs over a DC-isolated bus of the microcontroller interface.

Description

CLAIM OF PRIORITY This application is a continuation of U.S. patent application Ser. No. 18/064,099, entitled “DISTRIBUTED COULOMB COUNTER,” filed Dec. 9, 2022, (Attorney Docket No. 3867.891US1) which is a Continuation-in-Part of and claims the benefit of priority of Patent Cooperation Treaty (PCT) application filed in the China Intellectual Property Office as the PCT Receiving Office, PCT Application Serial No.: PCT/CN2021/137061, entitled “COULOMB COUNTER DEVICES AND METHODS,” filed on Dec. 10, 2021 (Attorney Docket No. 3867.891WO1), which are hereby incorporated by reference herein in their entirety. TECHNOLOGICAL FIELD The present disclosure relates to electronics, and more particularly, but not by way of limitation, to a coulomb counter that can determine charge transfer from a battery or other electrochemical energy storage system. BACKGROUND Modern systems can use coulomb counters to determine an amount of charge transfer from an energy storage system, such as a battery. Examples of such systems include industrial electronics, electric passenger cars, electric industrial trucks, and energy storage systems. The determination of charge transfer may help in determining one or more of a system power output, a remaining system power capacity, or a state of charge (SoC) or state of health (SoH) of an energy storage system. SUMMARY A coulomb counter may operate by integrating a measured current value over time to determine a measurement of charge transfer. The measured current value may be updated at recurring intervals, such as corresponding to the sampling frequency of an analog-to-digital converter (ADC). The integration of these discrete current measurements may be a discrete integration, which may be performed by multiplying a discrete current measurement by a length of time between current measurements. The accuracy of the charge transfer measurement may depend upon one or more of the frequency of the current measurement, the accuracy of the current measurement, the accuracy of the time measurement, and the proper handling of the current and time measurement data. The present inventors have recognized, among other things, that the frequency of the current measurement may be increased by using an analog front end (AFE) circuit that can sample recurrently, record results, and report recorded results back to a host microcontroller. The AFE may be able to sample more quickly than the host microcontroller. This can be due to the AFE having fewer parallel tasks or overhead tasks than the host microcontroller, or the AFE being located more closely to the charge transfer to be measured. The AFE may also attempt to increase the accuracy of current measurements, such as by using a programmable gain amplifier (PGA) to amplify the analog current signal before conversion to a digital measured current value. The PGA may be connected to an automatic gain control (AGC) circuit that attempts to keep the analog signal provided to the ADC above a low threshold, such as to increase the usable resolution of the ADC. The AGC may attempt to keep the ADC from receiving an analog signal higher than a maximum input of the ADC, such as to prevent the loss of data due to clipping or saturation of the ADC. The AGC may be located on the AFE circuit, such as to allow for a shorter response time between the signal provided to the ADC being outside a desired range and the adjustment of the PGA using the AGC. The present inventors have recognized, among other things, that the AFE circuit may have a less expensive or less accurate clock than the host microcontroller, which may make it desirable to offload at least a portion of the timing to the host microcontroller, such as may include offloading a portion of the timing used in charge transfer calculations. The host microcontroller may have a more accurate clock, such as a precision crystal oscillator. There may not be a shared clock signal between the AFE and the host microcontroller, such as due to a voltage level difference between the AFE and the host microcontroller. A voltage level difference may introduce a need for the use of one or more of a DC-isolated bus or level switching circuits for data and clock connections between the AFE and host microcontroller. DC-isolated buses may have restricted bandwidth, and level switching circuits may be one or more of expensive, power-hungry, or bulky. For these and other reasons, it may be desirable to use a message-based timing system to offload a portion of the timing from the AFE to the host microcontroller. The present inventors have recognized, among other things, that the communication connection, such as a DC-isolated bus, between the AFE and the host microcontroller may be one or more of low bandwidth, crowded with a number of communication messages, or unstable. Therefore, it may be desirable to make message-based communications between the AFE and host microcontroller more robust, such as by monitoring for failed messages and res