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US-20260126589-A1 - CO-PACKAGED OPTICS SYSTEMS THAT INCLUDE OPTICAL ENGINES AND METHODS OF MAKING THE SAME

US20260126589A1US 20260126589 A1US20260126589 A1US 20260126589A1US-20260126589-A1

Abstract

Optical engines and methods for fabricating optical engines. In embodiments, the optical engine includes a silicon substrate and a photonic component mounted on the silicon substrate. The photonic component includes an edge coupler and a coupling interface configured to interface with one or more external optical components. The edge coupler includes a photonic component edge at the coupling interface. The silicon substrate includes a substrate coupling edge at the coupling interface. The photonic component edge protrudes beyond the substrate coupling edge at the coupling interface.

Inventors

  • WEI-KANG LIU
  • Cheng-Tse Tang
  • Hau-yan Lu
  • Chun-Heng Chen
  • I-Chun WANG
  • Tsung-Hsueh Yang
  • Lee-Chuan Tseng

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Dates

Publication Date
20260507
Application Date
20241104

Claims (20)

  1. 1 . A method for fabricating a semiconductor package, the method comprising: mounting a photonic component on a silicon substrate, wherein: the photonic component comprises an edge coupler and a coupling interface configured to interface with an external optical component; the edge coupler comprises a first edge at the coupling interface; and the silicon substrate comprises a second edge at the coupling interface; and removing a portion of the silicon substrate such that the first edge protrudes beyond the second edge at the coupling interface.
  2. 2 . The method of claim 1 , comprising performing a facet etch and etching the silicon substrate to create a recess in the silicon substrate under the first edge.
  3. 3 . The method of claim 2 , wherein etching the silicon substrate comprises undercutting the silicon substrate using sulfur hexafluoride.
  4. 4 . The method of claim 3 , wherein undercutting the silicon substrate using sulfur hexafluoride forms a semicircular notch in the silicon substrate underneath the first
  5. 5 . The method of claim 1 , wherein etching the silicon substrate to create the recess in the silicon substrate under the first edge comprises undercutting the silicon substrate using tetramethylammonium hydroxide.
  6. 6 . The method of claim 1 , comprising dicing the silicon substrate to remove a portion of the silicon substrate by: forming at least one scribe line on the silicon substrate using a laser; and cleaving the silicon substrate along the scribe line to remove the portion of the silicon substrate.
  7. 7 . The method of claim 1 , wherein removing the portion of the silicon substrate comprises performing laser dicing.
  8. 8 . The method of claim 1 , comprising mounting an electronic integrated circuit on the silicon substrate adjacent to the photonic component.
  9. 9 . The method of claim 1 , comprising mounting an electronic integrated circuit on top of the photonic component.
  10. 10 . The method of claim 1 , wherein the edge coupler comprises a spot size converter (SSC), a buried oxide layer, and cladding.
  11. 11 . A semiconductor package comprising: a silicon substrate; and a photonic component mounted on the silicon substrate, wherein: the photonic component comprises an edge coupler and a coupling interface configured to interface with one or more external optical components; the edge coupler comprises a photonic component edge at the coupling interface; the silicon substrate comprises a substrate coupling edge at the coupling interface; the photonic component edge protrudes beyond the substrate coupling edge at the coupling interface; and a shape of the silicon substrate comprises a semicircular notch underneath the photonic component edge; and a conductive terminal providing an electrical connection for a ground or power supply voltage between the semiconductor package and an external component, wherein the conductive terminal includes a solder region and an intermetallic compound (IMC) region.
  12. 12 . The semiconductor package of claim 11 , wherein the coupling interface extends along a coupling plane, the substrate coupling edge comprises a recess portion distanced from the coupling plane by a first non-zero predetermined distance and an end portion distanced from the coupling plane by a second non-zero predetermined distance, and the first and second non-zero predetermined distances are different.
  13. 13 . The semiconductor package of claim 12 , wherein the edge coupler comprises a spot size converter (SSC), a buried oxide layer, and cladding.
  14. 14 . The semiconductor package of claim 11 , comprising an electronic integrated circuit mounted on the silicon substrate adjacent to the photonic component.
  15. 15 . The semiconductor package of claim 11 , comprising an electronic integrated circuit mounted on top of the photonic component.
  16. 16 . A photonic semiconductor package comprising: a silicon substrate; and a photonic component mounted on the silicon substrate, wherein the photonic component comprises an edge coupler and a coupling interface configured to interface with one or more external optical components, wherein the edge coupler comprises a photonic component edge at the coupling interface, wherein the silicon substrate comprises a substrate edge at the coupling interface, wherein, from a top view of the photonic semiconductor package, the edge coupler extends along a direction from a position above the silicon substrate to a position beyond the substrate edge, and wherein the width of the edge coupler decreases gradually along the direction.
  17. 17 . The photonic semiconductor package of claim 16 , comprising an electronic integrated circuit hybrid bonded to a top of the photonic component.
  18. 18 . The photonic semiconductor package of claim 17 , wherein the photonic component comprises one or more through-silicon vias (TSVs) electrically connecting one or more transistors of the electronic integrated circuit to an external component.
  19. 19 . The photonic semiconductor package of claim 18 , wherein the photonic component comprises one or more interconnect structures electrically connecting the TSVs to one or more conductive pads.
  20. 20 . The photonic semiconductor package of claim 19 , wherein the photonic component comprises one or more conductive terminals over the conductive pads.

Description

BACKGROUND Silicon photonics technology may be useful for high-speed data transmission and optical communication systems. One of the components in some of these optical communication systems is the edge coupler, which facilitates the efficient transfer of optical signals between silicon photonics devices of the optical communication system and external optical elements. These external elements typically include, for example, a fiber array unit (FAU) or a micro-optics lens, which may be used for directing and focusing the optical signals into and out of the silicon photonics chip. The integration of an effective edge coupler may aid in minimizing coupling losses and ensuring high-performance operation of the entire optical communication system. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A-1G illustrate an example co-packaged optics system including an embodiment optical engine. FIGS. 2A-2B are a vertical cross-sectional views of an alternative embodiment configuration for the optical engine. FIG. 3A-3E illustrate various intermediate structures that may be formed and used in an embodiment process for fabricating an optical engine having an edge coupler. FIGS. 4A-4E illustrate various intermediate structures that may be formed and used in an embodiment process for fabricating an optical engine having an edge coupler with a silicon nitride (SiN) spot size converter. FIGS. 5A-5D illustrate various intermediate structures that may be formed and used in another embodiment process for fabricating an optical engine having an edge coupler. FIGS. 6A-6D illustrate various intermediate structures that may be formed and used in another embodiment process for fabricating an optical engine having an edge coupler. FIGS. 7A-7D illustrate elements of an embodiment optical engine after removal of a silicon ledge. FIGS. 8A-8B illustrate various intermediate structures that may be formed and used in an embodiment process for aligning an edge coupler with an example optical component. FIG. 9 illustrates a flow diagram of an embodiment method for fabricating an optical engine. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range. Various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to particular examples and implementations are for illustrative purposes and are not intended to limit the scope of the claims. The fabrication of edge couplers in silicon photonics may present several technical challenges. These technical challenges include achieving precise alignment between the silicon waveguide and the external optical elements, as well as maintaining low insertion loss and high coupling efficiency over a broad wavelength range. Various methods have been proposed to address these issues, includ