US-20260126691-A1 - DISPLAY PANEL AND ARRAY SUBSTRATE THEREOF

US20260126691A1US 20260126691 A1US20260126691 A1US 20260126691A1US-20260126691-A1

Abstract

Display panels and array substrates thereof are disclosed, which comprise a substrate and a plurality of pixel units, wherein the substrate has two surfaces that are parallel and opposite to each other, the plurality of pixel units are disposed on the substrate, and at least one of the plurality of pixel units comprises an active element, a reflective structure, and an insulation structure, wherein the reflective structure has a reflective layer and a pixel electrode overlapping with each other and is adjacent to one of the two surfaces of the substrate, the insulation structure is disposed around the active element and has at least one conductive hole, and the active element and the pixel electrode are electrically connected to each other through the at least one conductive hole. This way, the impact of the manufacturing process on the production quality of the reflective layer can be effectively reduced.

Inventors

Yu-Chi CHIAO
I-tung Chen
Jhih Jie HUANG
Shih Chung LO
Chiung-Chang Wu

Assignees

HANNSTAR DISPLAY CORPORATION

Dates

Publication Date: 20260507
Application Date: 20250909
Priority Date: 20241101

Claims (20)

1 . An array substrate, comprising: a substrate having two surfaces parallel to each other; and a plurality of pixel units disposed on the substrate, at least one of the plurality of pixel units comprising: an active element; a reflective structure having a reflective layer and a pixel electrode disposed in a stacked manner, wherein the reflective structure is disposed adjacent to one of the two surfaces of the substrate; and an insulation structure disposed around the active element, wherein the insulation structure has at least one conductive hole, and the active element and the pixel electrode are electrically connected through the at least one conductive hole.
2 . The array substrate as claimed in claim 1 , wherein the pixel electrode is disposed on one side of the reflective layer facing the active element.
3 . The array substrate as claimed in claim 1 , wherein the active element comprises a semiconductor layer, a gate, a source, and a drain, wherein the semiconductor layer and the gate are stacked and insulated from each other, the source is electrically connected to the semiconductor layer, and the drain is electrically connected to the semiconductor layer and the pixel electrode.
4 . The array substrate as claimed in claim 1 , wherein the active element comprises a semiconductor layer, a gate, a source, and a drain, the semiconductor layer and the gate are stacked and insulated from each other, the semiconductor layer is electrically connected to the source and the drain, wherein the drain is electrically connected to the pixel electrode, and the drain and the reflective layer are arranged in a same layer.
5 . The array substrate as claimed in claim 3 , wherein the semiconductor layer comprises indium gallium zinc oxide (IGZO) or low-temperature polycrystalline silicon (LTPS).
6 . The array substrate as claimed in claim 1 , wherein the active element comprises a metal layer and an amorphous silicon (a-Si) semiconductor stacked and insulated from each other, the metal layer comprises a gate and the reflective layer insulated from each other, the gate and the amorphous silicon semiconductor overlap within a projection range of the substrate, a source and a drain are disposed on two opposite sides of the amorphous silicon semiconductor, the source and the drain are electrically connected to the amorphous silicon semiconductor, and the drain is electrically connected to the pixel electrode.
7 . The array substrate as claimed in claim 1 , wherein the reflective layer is disposed on one side of the substrate away from the active element, the substrate has a through hole, the through hole is in communication with the at least one conductive hole, and the active element and the pixel electrode are electrically connected through the at least one conductive hole and the through hole.
8 . The array substrate, as claimed in claim 7 , wherein the active element comprises a semiconductor layer and a gate, a source, and a drain are disposed on two opposite sides of the semiconductor layer, the source and the drain are electrically connected to the semiconductor layer, and the gate and the semiconductor layer are within the projection range of the substrate.
9 . The array substrate as claimed in claim 1 , wherein a buffer layer is disposed between the reflective structure and the substrate.
10 . The array substrate as claimed in claim 9 , wherein the buffer layer comprises at least two stacked buffer films.
11 . The array substrate as claimed in claim 9 , wherein a protective layer is disposed on one side of the reflective structure away from the substrate.
12 . The array substrate as claimed in claim 11 , wherein the protective layer comprises a light-transmitting material comprising a silicon-based compound, aluminum oxide (Al x O y ), or a combination thereof, wherein the silicon-based compound comprises one of silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ).
13 . The array substrate as claimed in claim 9 , wherein the buffer layer comprises a conductive material comprising indium tin oxide (ITO), indium zinc oxide (IZO), molybdenum (Mo), aluminum (Al), titanium (Ti), molybdenum oxide (MoO x ), aluminum oxide (AlO x ), titanium oxide (TiO x ), molybdenum aluminide (MoAl), or a combination thereof.
14 . The array substrate as claimed in claim 1 , wherein the reflective layer comprises a metal material, and the metal material comprises one of silver or aluminum.
15 . The array substrate as claimed in claim 1 , wherein a thickness of the reflective layer is greater than 900 angstroms (Å).
16 . The array substrate as claimed in claim 15 , wherein the thickness of the reflective layer ranges from 900 angstroms to 1200 angstroms.
17 . The array substrate as claimed in claim 1 , wherein one side of the reflective layer has surface microstructures.
18 . The array substrate, as claimed in claim 1 , wherein the insulation structure comprises a plurality of insulation material layers disposed in a stacked manner, and the plurality of insulation material layers comprises inorganic materials comprising silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), or a combination thereof.
19 . A display panel, comprising: an array substrate; a color filter substrate disposed opposite to the array substrate; and a display medium layer disposed between the array substrate and the color filter substrate; wherein the array substrate comprises a substrate and a plurality of pixel units, wherein the substrate has two surfaces parallel to each other, the plurality of pixel units are disposed on the substrate, and at least one of the plurality of pixel units comprises an active element, a reflective structure, and an insulation structure, the reflective structure has a reflective layer and a pixel electrode disposed in a stacked manner, wherein the reflective structure is disposed adjacent to one of the two surfaces of the substrate, the insulation structure is disposed around the active element, the insulation structure has at least one conductive hole, and the active element and the pixel electrode are electrically connected through the at least one conductive hole.
20 . The display panel as claimed in claim 19 , wherein the pixel electrode is disposed on one side of the substrate facing the display medium layer, the active element is disposed on one side of the substrate away from the display medium layer, the substrate has a through hole that is in communication with the at least one conductive hole, and the active element and the pixel electrode are electrically connected through the at least one conductive hole and the through hole.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims the priority of Taiwan Patent Applications No. 113142022, titled “DISPLAY PANEL AND ARRAY SUBSTRATE THEREOF,” filed on Nov. 1, 2024, the disclosures of which are incorporated herein by reference. FIELD OF THE INVENTION The present disclosure relates to a display device, specifically to display panels and array substrates thereof, suitable for a reflective display. BACKGROUND OF THE INVENTION Liquid crystal panels (LCD panels) can be roughly divided into transmissive type LCD panels, reflective type LCD panels, and transflective type LCD panels. Among them, the reflective type liquid crystal panel has a reflective layer that reflects incident ambient light to display the image. In addition to having high reflectivity in the visible spectrum range, the reflective layer's surface needs to be planarized and smooth to maintain the stability and reliability of the light reflection process. Although there have been some related technologies in the past, such as improving the planarization and smoothness of the reflective layer, if the mutual interference caused by adjacent film layers during the manufacturing process is not considered, it will still affect the manufacturing quality and needs to be improved. Given the above, it is necessary to provide a technical solution different from the prior art to solve the problems existing in conventional technology. SUMMARY OF THE INVENTION The object of the present disclosure is to provide a display panel and an array substrate thereof to effectively reduce the influence of the manufacturing process on the manufacturing quality of a reflective layer. To achieve the purpose mentioned above, one aspect of the present disclosure provides an array substrate, which includes: a substrate having two surfaces parallel to each other; and a plurality of pixel units disposed on the substrate, at least one of the plurality of pixel units comprising: an active element; a reflective structure having a reflective layer and a pixel electrode disposed in a stacked manner, wherein the reflective structure is disposed adjacent to one of the two surfaces of the substrate; and an insulation structure disposed around the active element, wherein the insulation structure has at least one conductive hole, and the active element and the pixel electrode are electrically connected through the at least one conductive hole. In some embodiments of the present disclosure, the pixel electrode is disposed on one side of the reflective layer facing the active element. In some embodiments of the present disclosure, the active element comprises a semiconductor layer, a gate, a source, and a drain, wherein the semiconductor layer and the gate are stacked and insulated from each other, the source is electrically connected to the semiconductor layer, and the drain is electrically connected to the semiconductor layer and the pixel electrode. In some embodiments of the present disclosure, the active element comprises a semiconductor layer, a gate, a source, and a drain, the semiconductor layer and the gate are stacked and insulated from each other, the semiconductor layer is electrically connected to the source and the drain, wherein the drain is electrically connected to the pixel electrode, and the drain and the reflective layer are arranged in a same layer. In some embodiments of the present disclosure, the semiconductor layer comprises indium gallium zinc oxide (IGZO) or low-temperature polycrystalline silicon (LTPS). In some embodiments of the present disclosure, the active element comprises a metal layer and an amorphous silicon (a-Si) semiconductor stacked and insulated from each other, the metal layer comprises a gate and the reflective layer insulated from each other, the gate and the amorphous silicon semiconductor overlap within a projection range of the substrate, a source and a drain disposed on two opposite sides of the amorphous silicon semiconductor, the source and the drain are electrically connected to the amorphous silicon semiconductor, and the drain is electrically connected to the pixel electrode. In some embodiments of the present disclosure, the reflective layer is disposed on one side of the substrate away from the active element, the substrate has a through hole, the through hole is in communication with the at least one conductive hole, and the active element and the pixel electrode are electrically connected through the at least one conductive hole and the through hole. In some embodiments of the present disclosure, the active element comprises a semiconductor layer and a gate, a source, and a drain are disposed on two opposite sides of the semiconductor layer, the source and the drain are electrically connected to the semiconductor layer, and the gate and the semiconductor layer are within the projection range of the substrate. In some embodiments of the present disclosure, a buffer layer is disposed between the reflectiv