US-20260126692-A1 - ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

Abstract

Disclosed are an array substrate, display panel, and display device; the array substrate includes: gate line groups, data lines, pixel electrodes, and the pixel electrodes includes: a first-type pixel electrode, and a second type pixel electrode, a light-shielding portion is on the same side of the substrate as the gate line group and is only in the area where the first type of pixel electrode is located, and the light-shielding portion includes: a first portion extending in the first direction, an orthographic projection of the first portion on the substrate passes through a central area of an orthographic projection of the first-type pixel electrode on the substrate.

Inventors

• Guozhi Wang
• Yuanhui Guo
• Yong Liu
• Wu Wang

Assignees

• CHENGDU BOE DISPLAY SCI-TECH CO., LTD.
• BOE TECHNOLOGY GROUP CO., LTD.

Dates

Publication Date

20260507

Application Date

20230329

Claims (20)

1. 1 - 36 . (canceled)
2. 37 . An array substrate, comprising: a substrate; a plurality of gate line groups on a side of the substrate, wherein the plurality of gate line groups extend along a first direction; a plurality of data lines on the same side of the substrate as the gate line groups; wherein the plurality of data lines extend along a second direction; a plurality of pixel electrodes on the same side of the substrate as the gate line groups and in an area formed by an intersection of the gate line groups and the data lines, wherein the plurality of pixel electrodes comprises: a first-type pixel electrode and a second-type pixel electrode; a light-shielding portion on the same side of the substrate as the gate line groups and only in an area where the first-type pixel electrode is located; wherein the light-shielding portion comprises: a first portion extending in the first direction; an orthographic projection of the first portion on the substrate passes through a central area of an orthographic projection of the first-type pixel electrode on the substrate.
3. 38 . The array substrate of claim 37 , wherein the light-shielding portion further comprises: a second portion that is on a side of the first portion and extends along the second direction; the second portion is connected with one end of the first portion, and an orthotropic projection of the second portion on the substrate overlaps with an orthographic projection of a side area of the first-type of pixel electrode on the substrate.
4. 39 . The array substrate of claim 37 , wherein the light-shielding portion further comprises: a third portion that is on the other side of the first portion and extends along the second direction; the third portion is connected with the other end of the first portion, and an orthotropic projection of the third portion on the substrate overlaps with an orthographic projection of the other side area of the first-type pixel electrode on the substrate.
5. 40 . The array substrate of claim 37 , wherein the first-type pixel electrode is a pixel electrode corresponding to a blue color resistance, and the second-type of pixel electrode comprises a pixel electrode corresponding to a red color resistance, or a pixel electrode corresponding to a green color resistance.
6. 41 . The array substrate of claim 39 , further comprises: a first signal wiring layer, wherein the light-shielding portion and the first signal wiring layer are on a same layer and of a same material; wherein the first signal wiring layer further comprises: a first common electrode wiring group extending along the second direction, wherein the first common electrode wiring group is disconnected at the gate line groups; the first common electrode wiring group comprises: two first common electrode wires extending along the second direction at different sides of each data line, and the light-shielding portion and the first common electrode wire close to the first-type pixel electrode in the first common electrode wiring group are integrated connection structure.
7. 42 . The array substrate of claim 41 , wherein the first signal wiring layer further comprises: a second common electrode wire extending along the first direction; a pixel electrode is provided between the second common electrode wire and the gate line group, and the second common electrode wire in a same extension direction is an integrated connection structure; there is a gap between the second portion and the second common electrode wire; and the first common electrode wire, the second common electrode wire, and the second portion form a first notch with an opening facing a side of the first-type pixel electrode.
8. 43 . The array substrate of claim 42 , wherein each gate line group comprises: a primary gate line and a secondary gate line; the first signal wiring layer further comprises: a third common electrode wire that is arranged at a side of the secondary gate line far away from the primary gate line, and extends along the first direction; there is the pixel electrode between the third common electrode wire and the second common electrode wire, and the third common electrode wire in a same extension direction is disconnected in an area where the data line is located; there is a gap between the third portion and the third common electrode wire; and the first common electrode wire, the third common electrode wire, and the third portion form a second notch with an opening facing a side of the pixel electrode.
9. 44 . The array substrate of claim 43 , wherein the third common electrode wire comprises: a first subsection and a second subsection located on a side of the first subsection far away from the second notch; a width of the first subsection in the second direction is greater than a width of the second subsection in the second direction.
10. 45 . The array substrate of claim 43 , wherein the first signal wiring layer further comprises: a fourth common electrode wire that is arranged on a side of the primary gate line far away from the secondary gate line, and extends along the first direction; there is the pixel electrode between the fourth common electrode wire and the second common electrode wire, and the fourth common electrode wire in a same extension direction is disconnected in an area where the data line is located; the array substrate further comprises: a first transistor connected with the data line and arranged on a side of the data line; the fourth common electrode wire comprises a notch group, the notch group comprises: a first notch located on a side of one data line, and a third notch located on the other side of the one data line and comprising an opening facing a side of the primary gate line, and the first notch and the first transistor are located on a same side of the one data line.
11. 46 . The array substrate of claim 45 , wherein the plurality of pixel electrodes comprise: a first pixel electrode row and a second pixel electrode row which extend along the first direction and are alternately arranged along the second direction; the first pixel electrode row is arranged on a side of the primary gate line far away from the secondary gate line, and the second pixel electrode row is arranged on a side of the secondary gate line far away from the primary gate line; the first pixel electrode row comprises a plurality of first pixel electrodes, and the second pixel electrode row comprises a plurality of second pixel electrodes.
12. 47 . The array substrate of claim 46 , wherein a layer where the data line is located further comprises: a first electrode of the first transistor electrically connected with the data line, and a first electrode portion arranged on a side of the first electrode of the first transistor; the first electrode portion comprises: a second electrode of the first transistor, a first lap portion electrically connected with the second electrode of the first transistor, and a second lap portion extending along the first direction from one end of the first lap portion; an orthographic projection of the first lap portion on the substrate overlaps with an orthographic projection of the first pixel electrode on the substrate, the first lap portion is electrically connected with the first pixel electrode through a first through hole, and an orthotropic projection of the second lap portion on the substrate overlaps with an orthographic projection of the fourth common electrode wire on the substrate to form a first capacitance; wherein the layer where the data line is located further comprises: a second electrode portion arranged on the other side of the first electrode of the first transistor; the second electrode portion comprises: a third electrode of the first transistor, a third lap portion, a first-transistor connection portion connecting the third electrode of the first transistor and the third lap portion, and a fourth lap portion extending along the first direction from one end of the third lap portion; an orthographic projection of the third lap portion on the substrate overlaps with an orthotropic projection of the second pixel electrode on the substrate, the third lap portion is electrically connected with the second pixel electrode through a second through hole; an orthotropic projection of the fourth lap portion on the substrate overlaps with an orthographic projection of the third common electrode wire on the substrate to form a second capacitance; wherein the layer where the data line is located further comprises: a third electrode portion arranged on a side of the second electrode portion facing the gate line group; the third electrode portion comprises: a second electrode of the second transistor and a fifth lap portion connected with the second electrode of the second transistor; an orthographic projection of the fifth lap portion on the substrate overlaps with the orthographic projection of the third common electrode wire on the substrate to form a third capacitance.
13. 48 . The array substrate of claim 47 , wherein a maximum width of the first lap portion in the second direction is greater than a maximum width of the second lap portion in the second direction; a maximum width of the third lap portion in the second direction is greater than a maximum width of the fourth lap portion in the second direction; and a maximum width of the fifth lap part in the second direction is greater than a maximum width of the second electrode of the second transistor in the second direction.
14. 49 . The array substrate of claim 47 , wherein the orthographic projection of the fifth lap portion on the substrate does not overlap with the orthographic projection of the fourth lap portion on the substrate.
15. 50 . The array substrate of claim 47 , wherein the first transistor comprises: a control electrode of the first transistor, an active layer of the first transistor, the first electrode of the first transistor, the second electrode of the first transistor and the third electrode of the first transistor; wherein the control electrode of the first transistor is a portion of the primary gate line; wherein the array substrate further comprises: a second transistor; the second transistor comprises: a control electrode of the second transistor, an active layer of the second transistor, a first electrode of the second transistor, the second electrode of the second transistor; wherein the control electrode of the second transistor is a portion of the secondary gate line, the first-transistor connection portion is multiplexed as the first electrode of the second transistor.
16. 51 . The array substrate of claim 45 , further comprises: a first wiring, a second wiring, and an adapter portion; there is a first insulating layer between the adapter portion and the first wiring, the first insulating layer comprises a third through hole; the third through hole exposes a part of the first wiring, and exposes a part of the substrate; there is a second insulating layer between the adapter portion and the second wiring, the second insulating layer comprises a fourth through hole; the fourth through hole exposes a part of the second wiring, and exposes a part of the substrate; one end of the adapter portion covers the third through hole, and contacts with the first wiring through the third through hole; the other end of the adapter portion covers the fourth through hole, and contacts with the second wiring through the fourth through hole; the adapter portion laps the first wiring with the second wiring; wherein the first wirings comprise the primary gate line, the secondary gate line, the data line, the first common electrode wire, the second common electrode wire, the third common electrode wire or the fourth common electrode wire; the second wire trace comprises: the primary gate line, the secondary gate line, the data line, the first common electrode wire, the second common electrode wire, the third common electrode wire or the fourth common electrode wire.
17. 52 . An array substrate, comprising: a substrate; a plurality of gate lines on a side of the substrate, and extending in a first direction; a plurality of data lines on the same side of the substrate as the gate lines, and extending along a second direction; a plurality of pixel electrodes on the same side of the substrate as the gate lines, and in areas formed by an intersection of the gate lines and the data lines; wherein each data line comprises a first data portion extending in the second direction, a second data portion extending in the second direction, and a third data portion extending along the first direction and connecting the first data portion with the second data portion; an extension line of the first data portion does not overlaps with an extension line of the second data portion; an orthographic projection of an extension line of the third data portion on the substrate passes through a central area of an orthographic projection of the pixel electrode on the substrate; an orthographic projection of the first data portion on the substrate overlaps with an orthographic projection of a first side area of the pixel electrode on the substrate; an orthotropic projection of the second data portion on the substrate overlaps with an orthographic projection of a second side area of the pixel electrode on the substrate.
18. 53 . The array substrate of claim 52 , further comprises: a second electrode of a transistor in a layer same as a layer where the data lines are located, and a first electrode block connected with the second electrode of the transistor; the first electrode block is arranged at a position between two adjacent third data portions; an orthographic projection of the first electrode block on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate, and the first electrode block is electrically connected with the pixel electrode through a fifth through hole; wherein the array substrate further comprises: a fifth common electrode wiring group; the fifth common electrode group comprises: two fifth common electrode wire extending along the first direction; a second electrode block is provided between two fifth common electrode wires in a same fifth common electrode wiring group, and an orthotropic projection of the second electrode block on the substrate overlaps with an orthotropic projection of the first common electrode block on the substrate to form a fourth capacitance.
19. 54 . A display panel, comprising the array substrate of claim 37 .
20. 55 . The display panel of claim 54 , further comprises: an opposing substrate opposite to the array substrate, wherein the opposing substrate is provided with a common electrode layer; wherein the display panel further comprises a liquid crystal layer arranged between the array substrate and the opposing substrate; the liquid crystal layer comprises four liquid crystal regions in an area where the pixel electrodes are located, and liquid crystal orientations in the liquid crystal regions are different.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The application is a National Stage of International Application No. PCT/CN2023/084610, filed Mar. 29, 2023, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD The present disclosure relates to the field of semiconductor technology, in particular to an array substrate, a display panel and a display device. BACKGROUND Thin Film Transistor-Liquid Crystal Display (TFT-LCD) has a variety of commonly used display modes, such as Twisted Nematic (TN) display mode, Vertically Alignment (VA) display mode, and Fringe Field Switching (FFS) display mode, as well as In-Plane Switching (IPS) display mode, etc. The VA mode has the advantages of better dark performance and better contrast compared with other display modes. SUMMARY Embodiments of the present disclosure provide an array substrate, including: a substrate;a plurality of gate line groups on a side of the substrate, and the plurality of gate line groups extend along a first direction;a plurality of data lines on the same side of the substrate as the gate line groups; the plurality of data lines extend along a second direction;a plurality of pixel electrodes on the same side of the substrate as the gate line groups, and in an area formed by an intersection of the gate line groups and the data lines, each of the plurality of pixel electrodes includes: a first-type pixel electrode and a second-type pixel electrode;a light-shielding portion on the same side of the substrate as the gate line groups, and only in an area where the first-type pixel electrode is located; the light-shielding portion includes: a first portion extending in the first direction; an orthographic projection of the first portion on the substrate passes through a central area of an orthographic projection of the first-type pixel electrode on the substrate. In some embodiments, the light-shielding portion further includes: a second portion that is on a side of the first portion and extends along the second direction; the second portion is connected with one end of the first portion, and an orthotropic projection of the second portion on the substrate overlaps with an orthographic projection of a side area of the first-type of pixel electrode on the substrate. In some embodiments, the light-shielding portion further includes: a third portion that is on the other side of the first portion and extends along the second direction; the third portion is connected with the other end of the first portion, and an orthotropic projection of the third portion on the substrate overlaps with an orthographic projection of the other side area of the first-type pixel electrode on the substrate. In some embodiments, the first-type pixel electrode is a pixel electrode corresponding to a blue color resistance, and the second-type of pixel electrode includes a pixel electrode corresponding to a red color resistance, or a pixel electrode corresponding to a green color resistance. In some embodiments, the array substrate further includes: a first signal wiring layer, and the light-shielding portion and the first signal wiring layer are on a same layer and of a same material. In some embodiments, the first signal wiring layer further includes: a first common electrode wiring group extending along the second direction, and the first common electrode wiring group is disconnected at the gate line groups; the first common electrode wiring group includes: two first common electrode wires extending along the second direction at different sides of each data line, and the light-shielding portion and the first common electrode wire close to the first-type pixel electrode in the first common electrode wiring group are integrated connection structure. In some embodiments, a width of the second portion in the first direction is 1˜3 times a width of the first common electrode wire in the first direction. In some embodiments, a width of the third portion in the first direction is approximately equal to a width of the second portion in the first direction. In some embodiments, a width of the first portion in the second direction is approximately equal to a width of the second portion in the first direction. In some embodiments, the first signal wiring layer further includes: a second common electrode wire extending along the first direction; a pixel electrode is provided between the second common electrode wire and the gate line group, and the second common electrode wire in a same extension direction is an integrated connection structure; there is a gap between the second portion and the second common electrode wire, and the first common electrode wire, the second common electrode wire, and the second portion form a first notch with an opening facing a side of the first-type pixel electrode. In some embodiments, each gate line group includes: a primary gate line and a secondary gate line; the first signal wiring layer further includes: a third common electrode wire that is