US-20260126718-A1 - Hybrid Inverse Lithography Technology Optimization

Abstract

The technology includes hybrid inverse lithography technology (ILT) optimization. According to one aspect, a method includes obtaining a target mask design for a semiconductor device to be fabricated. Based on a machine learning inverse lithography technology (ML ILT) model, a predicted ILT mask design corresponding to the target mask design is determined. An ILT optimization, using the predicted ILT mask design as an initialization point, is performed. Based on completion of the ILT optimization, a mask design is determined in order to fabricate the semiconductor device.

Inventors

• Abdalaziz I.M. Awad
• Cyrus Behroozi

Assignees

• GDM HOLDING LLC

Dates

Publication Date

20260507

Application Date

20250925

Claims (20)

1. 1 . A method comprising: obtaining, by one or more processors, a target mask design for a semiconductor device to be fabricated; determining, by one or more processors based on a machine learning inverse lithography technology (ML ILT) model, a predicted ILT mask design corresponding to the target mask design; performing, by one or more processors, an ILT optimization using the predicted ILT mask design as an initialization point; and generating, by one or more processors based on completion of the ILT optimization, a mask design in order to fabricate the semiconductor device.
2. 2 . The method of claim 1 , further comprising determining, by one or more processors, a mask pattern based on the mask design by simulating one or more lithographic processes.
3. 3 . The method of claim 1 , further comprising training, by one or more processors, the ML ILT model using a set of target mask designs and a set of mask designs based on the ILT optimization.
4. 4 . The method of claim 3 , wherein the set of target mask designs includes one or more mask designs from a standard cell library.
5. 5 . The method of claim 3 , wherein the set of target mask designs includes one or more augmented mask designs based on a standard cell library.
6. 6 . The method of claim 3 , wherein training the ML ILT model includes: determining, by one or more processors based on the ML ILT model, another predicted ILT mask design corresponding to a given target mask design of the set of target mask designs; and determining, by one or more processors, a level of difference between the other predicted ILT mask design and a given mask design of the set of mask designs corresponding to the given target mask design.
7. 7 . The method of claim 6 , further comprising determining, by one or more processors, whether the level of difference exceeds a threshold level of difference.
8. 8 . The method of claim 7 , further comprising, responsive to determining that the level of difference does not exceed the threshold level of difference, determining, by one or more processors, that the ML ILT model is fully trained.
9. 9 . The method of claim 1 , wherein the semiconductor device is a component of an integrated circuit (IC) device.
10. 10 . The method of claim 1 , wherein the semiconductor device is a component of at least one of a microelectromechanical systems (MEMS) device, a photonic device or a display device.
11. 11 . A system, comprising: memory configured to store at least one of a machine learning inverse lithography technology (ML ILT) model and a target mask design for a semiconductor device to be fabricated; and one or more processors operatively coupled to the memory, the one or more processors being configured to: determine, based on the ML ILT model, a predicted ILT mask design corresponding to the target mask design; perform an ILT optimization using the predicted ILT mask design as an initialization point; and generate, based on completion of the ILT optimization, a mask design in order to fabricate the semiconductor device.
12. 12 . The system of claim 10 , wherein the one or more processors are further configured to: simulate one or more lithographic processes using the mask design; and determine a mask pattern based on the simulation of the one or more lithographic processes.
13. 13 . The system of claim 10 , wherein: the memory is further configured to store a set of target mask designs and a set of mask designs based on the ILT optimization, and the one or more processors are further configured to train the ML ILT model using the set of target mask designs and the set of mask designs.
14. 14 . The system of claim 13 , wherein the set of target mask designs includes one or more mask designs from a standard cell library.
15. 15 . The system of claim 13 , wherein the set of target mask designs includes one or more augmented mask designs based on a standard cell library.
16. 16 . The system of claim 13 , wherein the one or more processors are configured to train the ML ILT model by being configured to: determine, based on the ML ILT model, another predicted ILT mask design corresponding to a given target mask design of the set of target mask designs; and determine a level of difference between the other predicted ILT mask design and a given mask design of the set of mask designs corresponding to the given target mask design.
17. 17 . The system of claim 16 , wherein the one or more processors are further configured to determine whether the level of difference exceeds a threshold level of difference.
18. 18 . The system of claim 17 , wherein the one or more processors are further configured to, responsive to a determination that the level of difference does not exceed the threshold level of difference, determine that the ML ILT model is fully trained.
19. 19 . The system of claim 11 , wherein the semiconductor device is a component of an integrated circuit (IC) device.
20. 20 . The system of claim 11 , wherein the semiconductor device is a component of at least one of a microelectromechanical systems (MEMS) device, a photonic device or a display device.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present application claims the benefit of and priority to U.S. Provisional Application No. 63/716,834, filed Nov. 6, 2024, the entire disclosure of which is hereby incorporated herein by reference. BACKGROUND Improving semiconductor processes and systems, and increasing yield from semiconductor processes and systems, may include modeling of many, if not all, processing steps associated with these semiconductor processes and systems. One such semiconductor process is lithography. Non-limiting examples of lithography processing steps include exposure, resist development, and mask-writing. Existing approaches may be subject to noise, optical diffraction, diffusion, and other lithography-related issues. This can create issues during fabrication of semiconductor devices, including those having large mask designs for advanced technology nodes. SUMMARY Inverse lithography technology (ILT) optimizations may be crucial for achieving viable semiconductor yield in advanced technology nodes. Lithography processes for these advanced technology nodes may have increasingly smaller process windows and/or increasingly problematic optical proximity effects. Conventional ILT optimizations can generate mask designs that are robust and manufacturable. Such optimizations may inversely optimize lithographic printing simulations by, for example, back propagating gradients of simulated loss with respect to a mask design (e.g., a perturbed mask design). Conventional ILT optimizations may be efficient for smaller mask designs. However, computational costs and/or inefficient scaling are challenges associated with using ILT models for advanced technology nodes. Requirements of a full simulation of mask designs for each step makes conventional ILT optimizations inefficient for scaling to larger mask designs. For instance, a complete conventional ILT optimization of mask designs for a large circuit layout (e.g., a full chip) may take several days, or even weeks, to perform using a significant amount of computer processing resources. Thus, such approaches are impractical for full chips due to weeks-long runtimes and the need for many accelerators to scale in parallel. Aspects of the technology disclosed herein include a hybrid approach to ILT optimization that leverages machine learning (ML) ILT models to improve the accuracy of ILT optimizations and/or increase acceleration to convergence of ILT optimizations. ML ILT models can be implemented, for example, using an image translation architecture (e.g., a U-Net or other neural network architecture). By way of example, a ML ILT model can be implemented using a convolutional neural network (CNN), a computer vision-oriented neural network, or a set of vision transformers. Mask designs output by trained ML ILT models, which can be output in just milliseconds, can be used to initialize subsequent ILT optimizations. Technical benefits of the disclosed technology include providing reduced (e.g., significantly reduced) computational requirements (e.g., computational resources, runtimes) relative to conventional ILT optimizations alone. Typical ILT optimizations are initialized with target mask designs, which are considerably far from mask designs ultimately generated by the ILT optimizations. In contrast, the disclosed technology uses ML ILT models to, in effect, replace initial iterations (e.g., the initial tens or hundreds of iterations) that would otherwise need to be performed. That is, the ML ILT models are trained to predict mask designs similar to mask designs that the ILT optimizations would have generated after those “replaced” iterations. Mask designs output by ML ILT models are also referred to herein as “predicted ILT mask designs”. Trained ML ILT models can output predicted ILT mask designs in a mere fraction of the time that it would take to perform those “replaced” iterations with accuracy. Initialization of ILT optimizations with predicted ILT mask designs reduces how many subsequent iterations of the ILT optimizations are performed. Even with the reduced quantity of iterations, the generated mask designs satisfy accuracy criteria. For example, how many iterations of the ILT optimizations are performed can be reduced by a factor of three. This is a significant technical benefit for the computing technology, as it reduces not only the amount of time required to generate a target design, but also reduces the amount of processing power and/or processing resources that would be required. The disclosed technology can include training ML ILT models using target mask designs and corresponding mask designs generated by ILT optimizations based on those target mask designs. Mask designs output by trained ML ILT models are accurately predictive of masks designs generated by ILT optimizations. However, in some instances, mask designs output by trained ML ILT models may not satisfy accuracy requirements across an entire layout. For example, the quali