US-20260126822-A1 - REGULATOR CIRCUIT FOR PARALLEL CONFIGURATION AND USER DEVICE INCLUDING THE SAME

US20260126822A1US 20260126822 A1US20260126822 A1US 20260126822A1US-20260126822-A1

Abstract

A regulator circuit includes a first linear regulator circuit, configured to control a voltage on an output node based on a first reference voltage and to provide first current to the output node, and a second linear regulator circuit, connected in parallel to the first linear regulator circuit and configured to provide second current to the output node, and the second linear regulator circuit is further configured to control a magnitude of the second current based on a magnitude of the first current.

Inventors

Hyeunseok NAM
SEONGMUN PARK

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251230
Priority Date: 20221223

Claims (20)

1 . A power management integrated circuit, comprising: a control circuit configured to generate a first control signal and a second control signal; and a regulator circuit electrically connected to the control circuit and configured to receive the first control signal and the second control signal, wherein the regulator circuit comprises, a first linear regulator circuit configured to generate a first voltage sensing feedback voltage corresponding to a voltage of an output node and to compensate a difference between a first reference voltage and the first voltage sensing feedback voltage in response to the first control signal; and a second linear regulator circuit configured to generate a second current sensing feedback voltage corresponding to a current of the output node and to compensate a difference between a second reference voltage and the second current sensing feedback voltage in response to the second control signal.
2 . The power management integrated circuit of claim 1 , wherein the first linear regulator circuit comprises: a first switching circuit configured to receive a first input voltage and a second input voltage and to select the first input voltage as the first reference voltage in response to the first control signal; and a second switching circuit configured to receive the first voltage sensing feedback voltage and a first current sensing feedback voltage and to select the first voltage sensing feedback voltage in response to the first control signal.
3 . The power management integrated circuit of claim 2 , wherein the second linear regulator circuit comprises: a third switching circuit configured to receive a second input voltage and the first current sensing feedback voltage and to select the first current sensing feedback voltage as the second reference voltage in response to the second control signal; and a fourth switching circuit configured to receive a second voltage sensing feedback voltage and the second current sensing feedback voltage and to select the second current sensing feedback voltage in response to the first control signal.
4 . The power management integrated circuit of claim 2 , wherein the first linear regulator circuit further comprises: a voltage compensator configured to generate a first error voltage based on the difference between the first reference voltage and the first voltage sensing feedback voltage.
5 . The power management integrated circuit of claim 4 , wherein the first linear regulator circuit further comprises: a first voltage divider connected between the output node and a ground terminal and configured to generate the first voltage sensing feedback voltage; a first power transistor connected between a power supply voltage terminal and the output node and configured to receive the first error voltage; a second power transistor connected between the power supply voltage terminal and a first current sensing node and configured to transmit current generated by mirroring the first current to the first current sensing node; and a first current sensing circuit connected between the first current sensing node and the ground terminal and configured to generate the first current sensing feedback voltage based on the current generated by mirroring the first current.
6 . The power management integrated circuit of claim 3 , wherein the second linear regulator circuit further comprises: a second voltage compensator configured to generate a second error voltage based on the difference between the second reference voltage and the second current sensing feedback voltage.
7 . The power management integrated circuit of claim 6 , wherein the second linear regulator circuit further comprises: a second voltage divider connected between the output node and a ground terminal and configured to generate the second voltage sensing feedback voltage; a third power transistor connected to a power supply voltage terminal and configured to receive the second error voltage; a fourth power transistor connected between the power supply voltage terminal and a second current sensing node and configured to output current generated by mirroring the second current to the second current sensing node; and a second current sensing circuit connected between the second current sensing node and the ground terminal and configured to generate the second current sensing feedback voltage based on the current generated by mirroring the second current.
8 . The power management integrated circuit of claim 7 , wherein the second linear regulator circuit further comprises: an offset controller configured to receive the second current sensing feedback voltage from one end connected to the second current sensing circuit to generate an offset voltage in the second current sensing feedback voltage, and to provide the second current sensing feedback voltage to the fourth switching circuit through the other end, the second current sensing feedback voltage reflecting the offset voltage.
9 . The power management integrated circuit of claim 8 , wherein the offset controller comprises a current source connected between the power supply voltage terminal and the other end, at least one resistor connected between the other end and at least one transistor; and the at least one transistor connected between the at least one resistor and the ground terminal, and the second current sensing feedback voltage is applied to a gate of the at least one transistor through the one end.
10 . The power management integrated circuit of claim 1 , wherein the first linear regulator circuit configured to control the voltage on the output node based on the first reference voltage and to provide the first current to the output node, the second linear regulator circuit connected in parallel to the first linear regulator circuit and configured to provide a second current to the output node, and the second linear regulator circuit is further configured to control a magnitude of the second current based on a magnitude of the first current.
11 . The power management integrated circuit of claim 10 , wherein the second linear regulator circuit is further configured to control the magnitude of the second current such that the first current is higher than the second current by a first value.
12 . A user device comprising: a power management integrated circuit configured to generate a power supply voltage; and an application processor configured to receive the power supply voltage from the power management integrated circuit, wherein the power management integrated circuit comprising: a control circuit configured to generate a first control signal and a second control signal; and a regulator circuit electrically connected to the control circuit and configured to receive the first control signal and the second control signal, wherein the regulator circuit comprises, a first linear regulator circuit configured to generate a first voltage sensing feedback voltage corresponding to a voltage of an output node and to compensate a difference between a first reference voltage and the first voltage sensing feedback voltage in response to the first control signal; and a second linear regulator circuit configured to generate a second current sensing feedback voltage corresponding to a current of the output node and to compensate a difference between a second reference voltage and the second current sensing feedback voltage in response to the second control signal.
13 . The user device of claim 12 , wherein the first linear regulator circuit comprises: a first switching circuit configured to receive a first input voltage and a second input voltage and to select the first input voltage as the first reference voltage in response to the first control signal; and a second switching circuit configured to the first voltage sensing feedback voltage and a first current sensing feedback voltage and to select the first voltage sensing feedback voltage from the first voltage sensing feedback voltage and the first current sensing feedback voltage in response to the first control signal.
14 . The user device of claim 13 , wherein the second linear regulator circuit comprises: a third switching circuit configured to receive the first input voltage and the first current sensing feedback voltage and to select the first current sensing feedback voltage as the second reference voltage in response to the second control signal; and a fourth switching circuit configured to receive a second voltage sensing feedback voltage and the second current sensing feedback voltage and to select the second current sensing feedback voltage from the second voltage sensing feedback voltage and the second current sensing feedback voltage in response to the first control signal.
15 . The user device of claim 13 , wherein the first linear regulator circuit further comprises: a voltage compensator configured to generate a first error voltage based on the difference between the first reference voltage and the first voltage sensing feedback voltage.
16 . The user device of claim 15 , wherein the first linear regulator circuit further comprises: a first voltage divider connected between the output node and a ground terminal and configured to generate the first voltage sensing feedback voltage; a first power transistor connected between a power supply voltage terminal and the output node and configured to receive the first error voltage; a second power transistor connected between the power supply voltage terminal and a first current sensing node and configured to transmit current generated by mirroring the first current to the first current sensing node; and a first current sensing circuit connected between the first current sensing node and the ground terminal and configured to generate the first current sensing feedback voltage based on the current generated by mirroring the first current.
17 . The user device of claim 14 , wherein the second linear regulator circuit further comprises: a second voltage compensator configured to generate a second error voltage based on the difference between the second reference voltage and the second current sensing feedback voltage.
18 . The user device of claim 17 , wherein the second linear regulator circuit further comprises: a second voltage divider connected between the output node and a ground terminal and configured to generate the second voltage sensing feedback voltage; a third power transistor connected to a power supply voltage terminal and configured to receive the second error voltage; a fourth power transistor connected between the power supply voltage terminal and a second current sensing node and configured to output current generated by mirroring the second current to the second current sensing node; and a second current sensing circuit connected between the second current sensing node and the ground terminal and configured to generate the second current sensing feedback voltage based on the current generated by mirroring the second current.
19 . The user device of claim 18 , wherein the second linear regulator circuit further comprises: an offset controller configured to receive the second current sensing feedback voltage from one end connected to the second current sensing circuit to generate an offset voltage in the second current sensing feedback voltage, and to provide the second current sensing feedback voltage to the fourth switching circuit through the other end, the second current sensing feedback voltage reflecting the offset voltage.
20 . An application processor comprising: circuitry configured to receive a power supply voltage from a power management integrated circuit through a power supply line, wherein the application processor is electrically connected to the power management integrated circuit through an output node, and wherein the power management integrated circuit comprising: a control circuit configured to generate a first control signal and a second control signal; and a regulator circuit electrically connected to the control circuit and configured to receive the first control signal and the second control signal, wherein the regulator circuit comprises, a first linear regulator circuit configured to generate a first voltage sensing feedback voltage corresponding to a voltage of the output node and to compensate a difference between a first reference voltage and the first voltage sensing feedback voltage in response to the first control signal; and a second linear regulator circuit configured to generate a second current sensing feedback voltage corresponding to a current of the output node and to compensate a difference between a second reference voltage and the second current sensing feedback voltage in response to the second control signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application is a Continuation of U.S. application Ser. No. 18/336,278, filed on Jun. 16, 2023, which claims benefit of priority to Korean Patent Application No. 10-2022-0183631, filed on Dec. 23, 2022, in the Korean Intellectual Property Office, the disclosure of each of which are incorporated herein by reference in their entirety. BACKGROUND The present disclosure relates to a regulator circuit for parallel configuration. A voltage regulator is used to provide a constant voltage to a circuit. A linear regulator is a type of voltage regulator and is used to stably supply power to various types of electronic devices. For example, a linear regulator may be used in a power management integrated circuit (PMIC) of a mobile device such as a smartphone or a tablet PC. SUMMARY Example embodiments provide a regulator circuit for reducing power loss while increasing output current. According to an example embodiment, a regulator circuit includes a first linear regulator circuit, configured to control a voltage on an output node based on a first reference voltage and to provide first current to the output node, and a second linear regulator circuit, connected in parallel to the first linear regulator circuit and configured to provide second current to the output node, and the second linear regulator circuit is further configured to control a magnitude of the second current based on a magnitude of the first current. According to an example embodiment, a regulator circuit includes a first linear regulator circuit to an n-th linear regular circuit, n being an integer greater than or equal to 3. The first linear regulator circuit to the n-th linear regulator circuit may be connected to an output node in parallel, and may respectively provide first current to n-th current to the output node. The first linear regulator circuit is configured to control a voltage on the output node based on a first reference voltage, and the second linear regulator circuit to the n-th linear regulator circuit are configured to control magnitudes of the second current to the n-th current based on a magnitude of the first current. According to an example embodiment, a linear regulator circuit includes a first voltage compensator configured to generate a first error voltage based on a difference between a first reference voltage and a first feedback voltage, a first power transistor connected between an output node and a power supply voltage terminal and configured to receive the first error voltage, a first switching circuit configured to select one of a plurality of input voltages in response to a selection control signal and to provide the first reference voltage to the voltage compensator, and a second switching circuit configured to provide either one of a voltage sensing feedback voltage and a first current sensing feedback voltage based on first current flowing to the output node as the first feedback voltage, the voltage sensing feedback voltage being a division of a voltage on the output node. According to an example embodiment, a user device includes a power management integrated circuit, configured to generate a power supply voltage, and an application processor configured to receive the power supply voltage from the power management integrated circuit. The power management integrated circuit may include a first linear regulator circuit to an n-th linear regulator circuit, n being an integer greater than or equal to 2, the first linear regulator circuit to the n-th linear regulator circuit may be connected to an output node in parallel and may respectively configured to provide first current to n-th current to the output node, the first linear regulator circuit configured to control a voltage on the output node based on a first reference voltage, and the second linear regulator circuit configured to the n-th linear regulator circuit may control second current to n-th current based on a magnitude of the first current. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings. FIG. 1 is a block diagram illustrating a user device according to an example embodiment. FIG. 2 is a diagram illustrating a linear regulator circuit according to an example embodiment. FIG. 3A is a diagram illustrating an example of a configuration and an operation of the linear regulator circuit of FIG. 2. FIG. 3B is a diagram illustrating another example of an operation of the linear regulator circuit of FIG. 3A. FIG. 4 is a diagram illustrating another example of a linear regulator circuit according to an example embodiment. FIG. 5 is a block diagram illustrating a user device according to an example embodiment. FIG. 6 is a diagram illustrating a regulator circuit including a parallel connection structure of a linear regulator according to t