US-20260126826-A1 - COMPACT HIGH FREQUENCY CLOCK GENERATION

US20260126826A1US 20260126826 A1US20260126826 A1US 20260126826A1US-20260126826-A1

Abstract

Described herein are apparatus and methods for compact high frequency clock generation. A high frequency clock generation circuit includes a differential frequency doubler configured to generate a differential F S /2 frequency clock from a differential F S /4 frequency clock using two input clock phases, and a multistage clock driver configured to at least correct asymmetry of the differential F S /2 frequency clock generated by the differential frequency doubler.

Inventors

Jerry Yee-Tung Lam
Douglas Stuart McPherson
Yuriy Greshishchev

Assignees

CIENA CORPORATION

Dates

Publication Date: 20260507
Application Date: 20241101

Claims (20)

1 . A high frequency clock generation circuit, comprising: a differential frequency doubler configured to generate a differential F S /2 frequency clock from a differential F S /4 frequency clock using two clock phases as inputs; and a multistage clock driver configured to at least correct asymmetry of the differential F S /2 frequency clock generated by the differential frequency doubler.
2 . The high frequency clock generation circuit of claim 1 , further comprises a multiphase clock generation circuit configured to generate N/2 phase clocks at a F S /N clock frequency.
3 . The high frequency clock generation circuit of claim 2 , wherein the multiphase clock generation circuit is a low noise injection locked 8-phase ring oscillator.
4 . The high frequency clock generation circuit of claim 2 , further comprises a differential N/2-push frequency multiplier configured to generate the differential F S /4 frequency clock with the two phase clocks from the N/2 phase clocks.
5 . The high frequency clock generation circuit of claim 1 , wherein the differential frequency doubler further comprises a 2-push frequency multiplier configured to generate one clock phase of the differential F S /2 frequency clock from the differential F S /4 frequency clock; and a positive feedback gain structure configured to generate a second clock phase of the differential F S /2 frequency clock, wherein a resulting differential F S /2 frequency clock has input and output drive asymmetry.
6 . The high frequency clock generation circuit of claim 1 , wherein the multistage clock driver further comprises an input stage configured to correct the asymmetry of the differential F S /2 frequency clock generated by the differential frequency doubler and apply a high gain to output a low signal power differential F S /2 frequency clock; an intermediate stage configured to apply two stages of high gain to the low signal power differential F S /2 frequency clock and output an intermediate signal power differential F S /2 frequency clock; and an output stage configured to apply a low gain to the intermediate signal power differential F S /2 frequency clock to generate a high signal power differential F S /2 frequency clock.
7 . The high frequency clock generation circuit of claim 6 , wherein the multistage clock driver further comprises a first transformer configured to connect the input stage to the intermediate stage; a second transformer configured to connect the two stages of the intermediate stage; and a third transformer configured to connect the intermediate stage to the output stage, wherein the first transformer, the second transformer, and the third transformer are configured to provide compact impedance matching and maximize Q.
8 . The high frequency clock generation circuit of claim 6 , wherein the input stage further comprises a cascode circuit configured to provide high gain to the differential F S /2 frequency clock; and a positive feedback circuit connected to the cascode circuit and to the intermediate stage, the positive feedback circuit configured to correct the asymmetry in the differential F S /2 frequency clock.
9 . The high frequency clock generation circuit of claim 6 , wherein the output stage further comprises a cascode circuit configured to operate at saturation gain levels in order to limit output power variability and deliver consistent clock levels.
10 . A method for high frequency clock generation, comprising: generating, at a differential frequency doubler, a differential F S /2 frequency clock from a differential F S /4 frequency clock using two input clock phases; and correcting, at a multistage clock driver, asymmetry of the differential F S /2 frequency clock generated by the differential frequency doubler.
11 . The method for high frequency clock generation of claim 10 , further comprises applying, at the multistage clock driver, multiple gain stages to the differential F S /2 frequency clock generated by the differential frequency doubler to generate a low signal power differential F S /2 frequency clock.
12 . The method for high frequency clock generation of claim 10 , further comprises generating N/2 phase clocks at a F S /N clock frequency; and generating, by a differential N/2-push frequency multiplier, the differential F S /4 frequency clock with the two phase clocks from the N/2 phase clocks.
13 . The method for high frequency clock generation of claim 10 , further comprises generating, by a 2-push frequency multiplier, one clock phase of the differential F S /2 frequency clock from the differential F S /4 frequency clock; and generating, by a positive feedback gain structure, a second clock phase of the differential F S /2 frequency clock, wherein a resulting differential F S /2 frequency clock has input and output drive asymmetry.
14 . A device, comprising: a multiphase clock generation circuit configured to generate N/2 phase clocks at a F S /N clock frequency; a differential N/2-push frequency multiplier configured to generate differential F S /4 frequency clock with two phase clocks from the N/2 phase clocks; a differential frequency doubler configured to generate a differential F S /2 frequency clock from the differential F S /4 frequency clock using the two clock phases as inputs; and a multistage clock driver configured to at least correct asymmetry of the differential F S /2 frequency clock generated by the differential frequency doubler.
15 . The device of claim 14 , wherein the multiphase clock generation circuit is a low noise injection locked 8-phase ring oscillator.
16 . The device of claim 14 , wherein the differential frequency doubler further comprises a 2-push frequency multiplier configured to generate one clock phase of the differential F S /2 frequency clock from the differential F S /4 frequency clock; and a positive feedback gain structure configured to generate a second clock phase of the differential F S /2 frequency clock, wherein a resulting differential F S /2 frequency clock has input and output drive asymmetry.
17 . The device of claim 14 , wherein the multistage clock driver further comprises an input stage configured to correct the asymmetry of the differential F S /2 frequency clock generated by the differential frequency doubler and apply a high gain to output a low signal power differential F S /2 frequency clock; an intermediate stage configured to apply two stages of high gain to the low signal power differential F S /2 frequency clock and output an intermediate signal power differential F S /2 frequency clock; and an output stage configured to apply a low gain to the intermediate signal power differential F S /2 frequency clock to generate a high signal power differential F S /2 frequency clock.
18 . The device of claim 17 , wherein the multistage clock driver further comprises a first transformer configured to connect the input stage to the intermediate stage; a second transformer configured to connect the two stages of the intermediate stage; and a third transformer configured to connect the intermediate stage to the output stage, wherein the first transformer, the second transformer, and the third transformer are configured to provide compact impedance matching and maximize Q.
19 . The device of claim 17 , wherein the input stage further comprises a cascode circuit configured to provide high gain to the differential F S /2 frequency clock; and a positive feedback circuit connected to the cascode circuit and to the intermediate stage, the positive feedback circuit configured to correct the asymmetry in the differential F S /2 frequency clock.
20 . The device of claim 19 , wherein the output stage further comprises a cascode circuit configured to operate at saturation gain levels in order to limit output power variability and deliver consistent clock levels.

Description

TECHNICAL FIELD This disclosure relates to digital to electronic circuits. BACKGROUND The need for high-speed and high-performance electronic circuits is ever increasing. For example, the need for high-speed and high-performance digital to analog converters (DACs) in optical transceivers grows as the data rate in optical coherent modems increases. High-speed and high-performance DACs require high frequency clocks to convert a wide bus of parallel input data into a single high speed analog signal. However, the capacity of semiconductor technologies optimized for high-speed digital signal processing and data processing is lacking in terms of speed of operation, precision in timing, output linearity, and frequency response. Moreover, even if the technology is capable, the circuitry can be complex, occupy a larger portion of area, and have high power consumption. SUMMARY Described herein are apparatus and methods for compact high frequency clock generation. In an implementation, a high frequency clock generation circuit includes a differential frequency doubler configured to generate a differential FS/2 frequency clock from a differential FS/4 frequency clock using two input clock phases, and a multistage clock driver configured to at least correct asymmetry of the differential FS/2 frequency clock generated by the differential frequency doubler. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. FIG. 1 is a block diagram of an example of a high frequency clock generation circuit in accordance with embodiments of this disclosure. FIG. 2 is a block diagram of an example of a differential frequency doubler circuit in accordance with embodiments of this disclosure. FIG. 3 is a block diagram of an example of a multi-stage high frequency clock driver circuit in accordance with embodiments of this disclosure. FIG. 4 is a flowchart of an example technique for high frequency clock generation in accordance with embodiments of this disclosure. DETAILED DESCRIPTION Reference will now be made in greater detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings and the description to refer to the same or like parts. As used herein, the terminology “computer” or “computing device” includes any unit, or combination of units, capable of performing any method, or any portion or portions thereof, disclosed herein. The computer or computing device may include a processor. As used herein, the terminology “processor” indicates one or more processors, such as one or more special purpose processors, one or more digital signal processors, one or more microprocessors, one or more controllers, one or more microcontrollers, one or more application processors, one or more central processing units (CPU)s, one or more graphics processing units (GPU)s, one or more digital signal processors (DSP)s, one or more application specific integrated circuits (ASIC)s, one or more application specific standard products, one or more field programmable gate arrays, any other type or combination of integrated circuits, one or more state machines, or any combination thereof. As used herein, the terminology “memory” indicates any computer-usable or computer-readable medium or device that can tangibly contain, store, communicate, or transport any signal or information that may be used by or in connection with any processor. For example, a memory may be one or more read-only memories (ROM), one or more random access memories (RAM), one or more registers, low power double data rate (LPDDR) memories, one or more cache memories, one or more semiconductor memory devices, one or more magnetic media, one or more optical media, one or more magneto-optical media, or any combination thereof. As used herein, the terminology “instructions” may include directions or expressions for performing any method, or any portion or portions thereof, disclosed herein, and may be realized in hardware, software, or any combination thereof. For example, instructions may be implemented as information, such as a computer program, stored in memory that may be executed by a processor to perform any of the respective methods, algorithms, aspects, or combinations thereof, as described herein. Instructions, or a portion thereof, may be implemented as a special purpose processor, or circuitry, that may include specialized hardware for carrying out any of the methods, algorithms, aspects, or combinations thereof, as described herein. In some implementations, portions of the instructions may be distributed across multiple processors on a single d