US-20260126827-A1 - ADJUSTED-FREQUENCY SYNCHRONIZER FOR CLOCK DOMAIN CROSSING

US20260126827A1US 20260126827 A1US20260126827 A1US 20260126827A1US-20260126827-A1

Abstract

A synchronizer with flip-flops has a reduced number of flip-flops coupled in series, receiving as an input data of a first clock domain and supplying as an output data in the second clock domain. The second clock signal is at a variable frequency adjusted to a target frequency, by a division factor. The flip-flops are timed by a clock signal subsampling the second clock signal by a factor k1. The subsampled clock signal is generated by a frequency divider propagating a pulse of the signal every k1 clock pulses, while keeping the edges aligned.

Inventors

Jerome Lacan
Christophe Eva

Assignees

STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date: 20260507
Application Date: 20251024
Priority Date: 20241104

Claims (20)

1 . A device, comprising: a set of first flip-flops coupled in series, receiving first data in a first clock domain based on a first clock signal; and a clock adjustment circuit including: an input configured to receive a second clock signal asynchronous with the first clock signal; adjustment circuitry configured to generate an adjusted clock signal having a period larger than a period of the second clock signal; and an output coupled to a clock input of each of the flip-flops and configured to provide the adjusted clock signal to the clock input of each of the first flip-flops, wherein the set of first flip-flops is configured to output the first data in a second clock domain asynchronous with the first clock domain and based on the second clock signal.
2 . The device according to claim 1 , wherein the adjustment circuitry includes a subsampler configured to subsample the second clock signal by a subsampling factor, an integer greater than or equal to 2, the subsampler receiving, as input signal, the second clock signal and outputting the adjusted clock signal.
3 . The circuit according to claim 2 , wherein the adjustment circuit includes a clock divider upstream from the subsampler and configured to adjust the second clock signal by a division factor corresponding to an integer greater than or equal to 2.
4 . The device according to claim 3 , wherein the subsampler includes a module for adapting the subsampling factor to an adjustment of a frequency of the second clock signal by the division factor.
5 . The device according to claim 2 , wherein the subsampler comprises a counter configured to count pulses of the second clock signal and a clock gating cell coupled to the counter.
6 . The device according to claim 1 , wherein the set of flip-flops includes only two flip-flops in series.
7 . The device according to claim 1 , wherein, when a mean time between failures formula links a theoretical number N sync of flip-flops to a first frequency of the first clock signal and a second frequency of the second clock signal, a subsampling factor k is fixed at a factor k2 selected from the factors of N sync −1.
8 . The device according to claim 1 , wherein the adjustment circuit includes a clock divider configured to generate the adjusted clock signal by dividing the second clock signal by a division factor corresponding to an integer greater than or equal to 2.
9 . The device according to claim 1 , comprising a set of second flip-flops coupled in series and receiving second data in a third clock domain based on a third clock signal and each having a clock input coupled to receive the adjusted clock signal from the clock adjustment circuit, wherein the clock adjustment causes the second flip-flops to output the second data in the second clock domain, the third clock domain being asynchronous with the second clock domain.
10 . A method for synchronization between a first clock domain timed by a first clock signal and a second clock domain asynchronous with the first clock domain and timed by a second clock signal, the method comprising: obtaining at least one clock-division factor or clock-subsampling factor; adjusting, based on the clock-division factor, a variable frequency of the second clock signal at a target frequency to supply an adjusted clock signal timing the flip-flops; and controlling, with the adjusted clock signal, flip-flops put in series in a synchronization unit that receives as an input data of the first clock domain and supplies as an output data in the second clock domain.
11 . The method of claim 10 , wherein adjusting the variable frequency includes generating the adjusted clock signal by dividing the second clock signal with a frequency divider.
12 . The method of claim 10 , wherein adjusting the variable frequency includes generating the adjusted clock signal by subsampling the second clock signal with a subsampler.
13 . The method of claim 10 , wherein adjusting the variable frequency includes generating the adjusted clock signal by dividing a frequency of the second clock signal with a frequency divider and subsampling the output of the frequency divider with a subsampler.
14 . A method, comprising receiving, with a set of first flip-flops coupled in series, first input data in a first clock domain based on a first clock signal; receiving, with a clock adjustment circuit, a second clock signal asynchronous with the first clock signal; generating, with the clock adjustment circuit, an adjusted clock signal having a period larger than a period of the second clock signal; and providing the adjusted clock signal to a clock input of each of the first flip-flops; and outputting the first input data from the set of first flip-flops in a second clock domain based on the second clock signal.
15 . The method of claim 14 , wherein generating the adjusted clock signal includes dividing the second clock signal with a frequency divider of the frequency adjustment circuit.
16 . The method of claim 14 , wherein generating variable frequency includes subsampling the second clock signal with a subsampler of the clock adjustment circuit.
17 . The method of claim 16 , wherein the subsampler includes a counter configured to count pulses of the second clock signal and a clock gating cell coupled to the counter.
18 . The method of claim 14 , wherein the set of first flip-flops includes only two first flip-flops in series.
19 . The method of claim 14 , wherein generating the variable frequency includes generating a divided clock signal by dividing the frequency of the second clock signal with a frequency divider and subsampling the output of the frequency divider with a subsampler.
20 . The method of claim 11 , further comprising: receiving, with a set of second flip-flops coupled in series, second data in a third clock domain based on a third clock signal; providing the adjusted clock signal to a clock input of each of the second flip-flops; and outputting the second data from the set of second flip-flops in the second clock domain, the second clock domain being asynchronous with the first clock domain.

Description

BACKGROUND Technical Field Embodiments and implementations relate to the field of synchronizing data in systems having asynchronous time domains. Description of the Related Art A digital system is often composed of several digital subsystems. When these digital subsystems operate synchronously with the same clock, synchronizing the signals circulating between these digital subsystems is not necessary. On the other hand, if these digital subsystems are asynchronous, i.e., operating with clocks that are asynchronous at least in phase, the signals circulating between these digital subsystems must be synchronized. For example, a computer system may operate at a given frequency whereas the processor may operate at another frequency. An interface circuit that enables data to be transferred from one clock domain to another is called a synchronization unit or “synchronizer.” FIG. 1 illustrates a synchronizer with flip-flops 100 according to the prior art for synchronizing a data signal SIG_1. The flip-flop A 105 operates in the original clock domain A 107. The set of flip-flops B operates in the target clock domain B 114. In a known manner, a flip-flop is a logic circuit using an operator between its inputs and maintaining the values of its output or outputs-evaluated at a clock edge-during the clock cycle. The clock domain A 107 and the clock domain B 114 are asynchronous clock domains. The flip-flop A 105 receives the input signal SIG_1 at the data input “d” and is timed at a first clock frequency fA, by the first clock signal CLK_A at the clock input. FIG. 1 illustrates a set of four flip-flops B1 110, B2 111, B3 112 and B4 113 operating in series or “cascade” (the output “q” of the previous flip-flop supplying the input “d” of the following one). Another number of flip-flops can be envisaged. In particular, synchronizers with two flip-flops B are widely known. The input signal SIG_1 is transferred to the output “q” of the flip-flop A 105 by the action of the first clock signal CLK_A. The flip-flops of the set B are timed at a second clock frequency fB, by the second clock signal CLK_B, and the output signal at the output “q” of the flip-flop A 105 is transferred in series via each of the flip-flops in the set B as far as the final output “q” at the output node 120. If a clock source (for example fB) has a maximum operation frequency (fBmax), it can however be of variable frequency in the case where a user can adjust the frequency of the domain through a clock divider integrated in the clock source. FIG. 2 illustrates a time diagram 200 of the signals of the synchronizer 100. The following are shown: the signal A_q 205 at the output of the flip-flop A 105, i.e., at the input of the target clock domain B 114—, the clock signal CLK_B 207 of the target clock domain B 114, the signal B1_q 210 at the output of the first flip-flop B1 110, the signal B2_q 211 at the output of the following flip-flop B2 111, the signal B3_q 212 at the output of the again following flip-flop B3 112 and the signal B4_q 213 at the output of the last flip-flop B4 114. The signal B4_q corresponds here to the output signal OUTPUT 120. Each output signal Bi_q of an intermediate flip-flop Bi corresponds to the input signal B(i+1)_d of the following intermediate flip-flop B(i+1). There is a probability that, during the sampling of the signal A_q by the flip-flop B1 110 in the target clock domain 114, the output B1_q of the flip-flop B1 may go into a metastable state. This probability—which decreases over time—is illustrated symbolically by the shading after each edge. The following flip-flop B2 will have a smaller probability of doing the same (illustrated symbolically by the shading), and so on. These risks of metastable state depend on the parameters of the flip-flops and on the target frequency fB of the clock CLK_B. Putting the four flip-flops in series reduces this risk of metastable state at the output 120, at the cost of an offset sampling of a number of clock cycles corresponding to the number of additional flip-flops (for example with respect to a synchronizer with two flip-flops). The number Nsync of flip-flops B to be used is generally determined by the following formula: MTBF=et/trN·fA·fB·Tw where t, the resolution time, is equal to t=(Nsync-1)·(1fB-Tsetip-Tcp→q-Tuncertainty) MTBF is the mean time between failures. tr (resolution time of a flip-flop), TW (metastability window), N (total number of flip-flops in the synchronizer or synchronization system), Tsetup (duration of flip-flop setup), Tcp→q (latency time CP—clock pulse—at Q—output—of a flip-flop), Tuncertainty (constant) are fixed parameters, related to the flip-flops and/or to the circuit design selected. A greater number Nsync of flip-flops is prejudicial to the compactness of the synchronizer 100, as well as to the electrical consumption thereof. It also delays the conversion of the input signal SIG_1 in the target clock domain. To contain this number, it is necessary to im