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US-20260126844-A1 - SYSTEM ON CHIP POWER MODE MANAGEMENT FOR ORIGINAL EQUIPMENT MANUFACTURERS

US20260126844A1US 20260126844 A1US20260126844 A1US 20260126844A1US-20260126844-A1

Abstract

Systems, methods, and circuitries are provided for configuring and executing custom power modes for a system-on-chip (SoC). In one example, an SoC includes a memory and a processor. The memory is configured to store one or more power modes, wherein a power mode comprises a plurality of SoC component settings. At least one of the power modes comprises a custom power mode. The processor is configured to receive a request to switch from a first power mode to a second power mode; access the memory to determine SoC component settings associated with the second power mode; and provide configuration commands to SoC components based on the SoC component settings associated with the second power mode.

Inventors

  • Venkateswarlu Borra
  • Mario Mlynek
  • Adam Opielka
  • Lorenzo Marinelli

Assignees

  • INFINEON TECHNOLOGIES AG

Dates

Publication Date
20260507
Application Date
20241106

Claims (19)

  1. 1 . A custom power mode configuration system, comprising: a memory; and a processor, configured to obtain configuration of a custom power mode, wherein the configuration comprises a plurality of SoC component settings; determine whether the plurality of SoC component settings of the custom power mode violates a constraint; and when the plurality of SoC component settings does not violate a constraint, store the custom power mode in the memory.
  2. 2 . The custom power mode configuration system of claim 1 , wherein the constraint defines SoC component settings or combinations of SoC component settings that are prohibited.
  3. 3 . The custom power mode configuration system of claim 1 , wherein the plurality of SoC components comprise one or more of clock circuitry, central processing unit (CPU), memory region, a power domain comprising a set of SoC components, or a peripheral component.
  4. 4 . The custom power mode configuration system of claim 1 , wherein the memory is configured to store, for each custom power mode, a plurality of configuration files associated with respective SoC components, wherein the configuration file for a given SoC component defines values for SoC component settings of the given SoC component.
  5. 5 . A system-on-chip (SoC), comprising: a memory configured to store one or more power modes, wherein a power mode comprises a plurality of SoC component settings, further wherein at least one of the power modes comprises a custom power mode; and a processor, configured to receive a request to switch from a first power mode to a second power mode; access the memory to determine SoC component settings associated with the second power mode; and provide configuration commands to SoC components based on the SoC component settings associated with the second power mode.
  6. 6 . The SoC of claim 5 , wherein the processor is further configured to verify that the SoC component settings of the second power mode are feasible; and perform a fallback action when any of the SoC component settings of the second power mode are note feasible.
  7. 7 . The SoC of claim 5 , wherein the processor is further configured to determine an intermediate power mode comprising a plurality of SoC component settings associated with the switch from the first power mode to the second power mode; and provide configuration commands to SoC components based on the intermediate power mode prior to providing the configuration commands to the SoC components based on the SoC component settings of the second power mode.
  8. 8 . The SoC of claim 7 , wherein the processor is further configured to verify that the SoC component settings of the intermediate power mode are feasible; perform a fallback action when any of the SoC component settings of the intermediate power mode are not feasible; once in the intermediate power mode, verify that the SoC component settings of the second power mode are feasible; and perform a fallback action when any of the SoC component settings of the second power mode are not feasible.
  9. 9 . The SoC of claim 5 , wherein the SoC components comprise one or more of clock circuitry, central processing unit (CPU), memory region, a power domain comprising a set of SoC components, or a peripheral component.
  10. 10 . The SoC of claim 5 , wherein the memory is configured to store, for each custom power mode, a plurality of configuration files associated with respective SoC components, wherein the configuration file for a given SoC component defines values for SoC component settings of the given SoC component.
  11. 11 . A method, comprising providing configuration information defining one or more power modes, wherein a power mode comprises a plurality of SoC component settings, further wherein at least one of the power modes comprises a custom power mode; receiving a request to switch from a first power mode to a second power mode; determining SoC component settings associated with the second power mode based on the configuration information defining the second power mode; and providing configuration commands to SoC components based on the determined SoC component settings.
  12. 12 . The method of claim 11 , further comprising verifying that the SoC component settings of the second power mode are feasible; and performing a fallback action when any of the SoC component settings of the second power mode are note feasible.
  13. 13 . The method of claim 11 , further comprising determining an intermediate power mode associated with the switch from the first power mode to the second power mode; and providing intermediate configuration commands to SoC components based on the intermediate power mode prior to providing the configuration commands to the SoC components based on the SoC component settings of the second power mode.
  14. 14 . The method of claim 13 , further comprising verifying that SoC component settings of the intermediate power mode are feasible; performing a fallback action when any of the SoC component settings of the intermediate power mode are not feasible; once in the intermediate power mode, verifying that the SoC component settings of the second power mode are feasible; and performing a fallback action when any of the SoC component settings of the second power mode are not feasible.
  15. 15 . The method of claim 11 , wherein the SoC components comprise one or more of clock circuitry, central processing unit (CPU), memory region, a power domain comprising a set of SoC components, or a peripheral component.
  16. 16 . The method of claim 11 , wherein the configuration information comprises configuration files associated with respective SoC components, wherein the configuration file for a given SoC component defines values for SoC component settings of the given SoC component.
  17. 17 . The method of claim 11 , further comprising compiling the configuration information by obtaining configuration of a custom power mode, wherein a custom power mode comprises a plurality of SoC component settings; determining whether the plurality of SoC component settings of the custom power mode violates a constraint; and when the plurality of SoC component settings does not violate a constraint, storing the custom power mode in a memory.
  18. 18 . The method of claim 17 , wherein the constraint defines SoC component settings or combinations of SoC component settings that are prohibited.
  19. 19 . The method of claim 17 , comprising storing, for each custom power mode, a plurality of configuration files associated with respective SoC components, wherein the configuration file for a given SoC component defines values for SoC component settings of the given SoC component.

Description

FIELD The present disclosure relates generally to the field of processors and in particular to a system-on-chip (SoC) that provides different power consumption modes. BACKGROUND SoCs include many components and software related functions that may be capable of operating in different modes with respect to power consumption. Often, higher performance modes will result in higher power consumption whilst power saving modes may limit available functionality. BRIEF DESCRIPTION OF THE DRAWINGS Some examples of circuits, apparatuses and/or methods will be described in the following by way of example only. In this context, reference will be made to the accompanying Figures. FIG. 1 illustrates relative power consumption amongst multiple SoC power modes. FIG. 2 illustrates an example SoC, in accordance with various aspects described. FIG. 3 illustrates an example custom power mode system, in accordance with various aspects described. FIG. 4 illustrates operation of an example mode validation circuitry, in accordance with various aspects described. FIG. 5 illustrates operation of an example mode management circuitry, in accordance with various aspects described. DETAILED DESCRIPTION The present disclosure is described with reference to the attached figures. Similar components in various figures may be represented by similar reference characters. The figures are not drawn to scale and they are provided merely to illustrate the disclosure. Several aspects of the disclosure are described below with reference to example applications for illustration. Numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the selected present disclosure. Power management of a system on chip (SoC) is an important key performance indicator in many application contexts, including electric vehicles. With respect to power consumption, SoCs may provide a limited number of standard or default power modes. As indicated by the solid circles in FIG. 1, an example SoC may provide an active mode that consumes a maximum amount of power and exhibits maximum performance and a low power or sleep mode that consumes very little power and supports only minimal SoC functionality. Designers that integrate the SoC into a particular vehicle will install power management software and/or circuitry in the SoC that determines an operating mode of the electric vehicle and triggers or requests the SoC to operate in one of its standard power modes. Each electric vehicle manufacturer defines its own operating modes like Driving, Charging, On-Grid Parking, Off-Grid Parking, and so on based on certain vehicle operating parameters. When only a few standard power modes are provided by an SoC, a designer may be forced to trigger or request a relatively high power consumption SoC standard mode for a vehicle operating mode that requires just a few active SoC components or that can tolerate lower SoC performance. Thus, it may be desirable for an SoC to provide more standard power modes so that a designer may choose a standard power mode that minimizes power consumption while providing the needed performance for each operating mode. However, providing additional standard power modes for an SoC that meet the needs of multiple manufacturers is not a simple solution. This is because the different operating modes as defined by different manufactures may have different power consumption limitations and performance needs. FIG. 2 is a block diagram of an example SoC 200 that illustrates several example SoC components that may be enabled/disabled and/or have multiple modes of operation that may affect the power consumption of the SoC. The SoC components include one or more central processing unit (CPU) domains 202 that each include a set of hardware components such as a CPU core, digital signal processing (DSP) block and dedicated random access memory (RAM). The CPU domains may be independently enabled or disabled. When a CPU domain is disabled, its core, DSP block, and RAM may be powered down or placed in an inactive mode, while retaining current memory state. In addition to the CPU being enabled/disabled, the CPU domains may also be capable of operating in different performance modes (e.g., different DSP functionality may be enable/disabled) in which lower performance is provided but with less power consumption. The SoC 200 includes memory that is partitioned into multiple partitions or regions 204. Each memory region may be independently enabled/disabled. Clock circuitry 206 provides clock signals to SoC components. The clock circuitry 206 may include multiple clock sources. For example, the clock circuitry 206 may include one or more clock sources