US-20260126846-A1 - POWER REDUCTION DEVICE AND POWER REDUCTION METHOD

US20260126846A1US 20260126846 A1US20260126846 A1US 20260126846A1US-20260126846-A1

Abstract

A power reduction device includes a first master controller, a processor, and a power manager. The power manager includes a model acceleration algorithm. The first master controller is configured to output a first active transmission signal. The model acceleration algorithm is configured to control the clock source of the processor or the power supply of the processor to reduce the power consumption of the processor according to the first active transmission signal.

Inventors

Cheng-Chieh Wang

Assignees

NUVOTON TECHNOLOGY CORPORATION

Dates

Publication Date: 20260507
Application Date: 20251001
Priority Date: 20241107

Claims (18)

1 . A power reduction device, comprising: a first master controller, configured to output a first active transmission signal; a processor; and a power manager, comprising: a model acceleration algorithm, configured to control a clock source of the processor or a power supply of the processor to reduce a power consumption of the processor according to the first active transmission signal.
2 . The power reduction device as claimed in claim 1 , wherein the first active transmission signal comprises one of a peripheral direct memory access signal and a direct memory access signal; wherein the first master controller comprises one of a direct memory access controller and a peripheral direct memory access controller; wherein the power reduction device comprises a microcontroller, and the processor is disposed within the microcontroller.
3 . The power reduction device as claimed in claim 1 , wherein the power manager further comprises an event fusion engine; wherein the event fusion engine is configured to outputs an integrated signal according to a plurality of signals; wherein the plurality of signals comprises the first active transmission signal.
4 . The power reduction device as claimed in claim 3 , wherein the power manager further comprises a neural network inference engine; wherein the neural network inference engine outputs a first relay signal or a second relay signal according to the integrated signal and the model acceleration algorithm.
5 . The power reduction device as claimed in claim 4 , wherein the power manager further comprises a clock control logic; wherein the clock control logic adjusts a clock frequency of the processor according to the first relay signal.
6 . The power reduction device as claimed in claim 4 , wherein the power manager further comprises a power supply control logic; wherein the power supply control logic adjusts a voltage of the processor according to the second relay signal.
7 . The power reduction device as claimed in claim 1 , wherein the power reduction device is used for a first platform and/or a second platform.
8 . The power reduction device as claimed in claim 7 , wherein the model acceleration algorithm reduces the power consumption of the processor according to a first event of the first platform.
9 . The power reduction device as claimed in claim 8 , wherein the model acceleration algorithm reduces the power consumption of the processor according to a second event of the second platform; wherein the first platform and the second platform are different from each other.
10 . A power reduction method, comprising: outputting a first active transmission signal by a first master controller; outputting a second active transmission signal by a second master controller; reducing a power consumption of a processor according to the first active transmission signal controls a clock source of the processor or a power supply of the processor; and reducing the power consumption of the processor according to the second active transmission signal controls the clock source of the processor or the power supply of the processor; wherein the first active transmission signal and the second active transmission signal are not directly input to the processor; wherein each of the first master controller and the second master controller comprises one of a direct memory access controller and a peripheral direct memory access controller.
11 . The power reduction method as claimed in claim 10 , wherein the power reduction method is executed by a microcontroller; wherein the processor, the first master controller, and the second master controller are disposed within the microcontroller.
12 . The power reduction method as claimed in claim 10 , wherein a power manager further comprises an event fusion engine; wherein the event fusion engine is configured to outputs an integrated signal according to a plurality of signals; wherein the plurality of signals comprises the first active transmission signal; wherein the first active transmission signal comprises one of a peripheral direct memory access signal and a direct memory access signal.
13 . The power reduction method as claimed in claim 12 , wherein the power manager further comprises a neural network inference engine; wherein the neural network inference engine outputs a first relay signal or a second relay signal according to the integrated signal and a model acceleration algorithm.
14 . The power reduction method as claimed in claim 13 , wherein the power manager further comprises a clock control logic; wherein the clock control logic adjusts a clock frequency of the processor according to the first relay signal.
15 . The power reduction method as claimed in claim 13 , wherein the power manager further comprises a power supply control logic; wherein the power supply control logic adjusts a voltage of the processor according to the second relay signal.
16 . The power reduction method as claimed in claim 10 , wherein the power reduction method is used for a first platform and/or a second platform.
17 . The power reduction method as claimed in claim 16 , wherein a model acceleration algorithm reduces the power consumption of the processor according to a first event of the first platform and/or a second event of the second platform.
18 . The power reduction method as claimed in claim 17 , wherein the first platform and the second platform are different from each other.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This Application claims priority of TW Patent Application No. 113142720, filed on November 07, 2024, the entirety of which is incorporated by reference herein. BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a reduction device and reduction method, and, in particular, it is related to a power reduction device and power reduction method. Description of the Related Art Currently, in low power consumption (low power) designs of microcontrollers (MCUs) and microprocessors (MPUs), software developers are required to have a certain level of familiarity with the voltage and power supply control of the target platform. As a result, software developers need to spend time studying the specification sheets during program development, which also leads to more complex control-related code that is prone to unexpected errors, thereby increasing development costs and development time. BRIEF SUMMARY OF THE INVENTION The summary of the invention is intended to provide a simplified overview of the present disclosure so that readers may have a basic understanding of the disclosure. This summary is not an exhaustive overview of the disclosure, nor is it intended to identify essential or key elements of the embodiments of the invention, or to define the scope of the invention. An embodiment of the present invention provides a power reduction device. The power reduction device includes a first master controller, a processor, and a power manager. The power manager includes a model acceleration algorithm. The first master controller is configured to output a first active transmission signal. The model acceleration algorithm is configured to control a clock source of the processor or a power supply of the processor to reduce a power consumption of the processor according to the first active transmission signal. In one embodiment, the first active transmission signal includes one of a peripheral direct memory access signal and a direct memory access signal; wherein the first master controller includes one of a direct memory access controller and a peripheral direct memory access controller; wherein the power reduction device includes a microcontroller, and the processor is disposed within the microcontroller. In one embodiment, the power manager further includes an event fusion engine; wherein the event fusion engine is configured to outputs an integrated signal according to a plurality of signals; wherein the plurality of signals includes the first active transmission signal. In one embodiment, the power manager further includes a neural network inference engine; wherein the neural network inference engine outputs a first relay signal or a second relay signal according to the integrated signal and the model acceleration algorithm. In one embodiment, the power manager further includes a clock control logic; wherein the clock control logic adjusts a clock frequency of the processor according to the first relay signal. In one embodiment, the power manager further includes a power supply control logic; wherein the power supply control logic adjusts a voltage of the processor according to the second relay signal. In one embodiment, the power reduction device is used for a first platform and a second platform; wherein the model acceleration algorithm reduces the power consumption of the processor according to a first event of the first platform. In one embodiment, the model acceleration algorithm reduces the power consumption of the processor according to a second event of the second platform; wherein the first platform and the second platform are different from each other. Other embodiment of the present invention provides a power reduction method. The power reduction method includes the following steps: outputting a first active transmission signal by a first master controller; outputting a second active transmission signal by a second master controller; reducing a power consumption of the processor according to the first active transmission signal controls a clock source of the processor or a power supply of the processor; and reducing the power consumption of the processor according to the second active transmission signal controls the clock source of the processor or the power supply of the processor. The first active transmission signal and the second active transmission signal are not directly input to the processor. Each of the first master controller and the second master controller includes one of a direct memory access controller and a peripheral direct memory access controller. In one embodiment, the power reduction method is executed by a microcontroller; wherein the processor, the first master controller, and the second master controller are disposed within the microcontroller. In one embodiment, the power manager further comprises an event fusion engine; wherein the event fusion engine is configured to outputs an integrated signal according to a plu