US-20260126911-A1 - METHODS AND APPARATUSES FOR OPERATING A MEMORY DEVICE

Abstract

Example memory devices, memory systems, and methods for identifying zero pages in a memory device are disclosed. In one example, a method of operating a memory device includes performing, based on a first read voltage, a read operation on memory cells coupled to a word line of the memory device; determining a quantity of failed memory cells, the failed memory cells being memory cells having threshold voltages lower than the first read voltage; and in response to determining that the quantity of the failed memory cells is less than a threshold, ending the read operation.

Inventors

• Xingwei Tang
• Lu Guo
• Zhuqin DUAN
• Wen Luo
• Kun Ren

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260507

Application Date

20250114

Claims (20)

1. 1 . A method of operating a memory device, comprising: performing, based on a first read voltage, a read operation on memory cells coupled to a word line of the memory device; determining a quantity of failed memory cells, wherein the failed memory cells are memory cells having threshold voltages lower than the first read voltage; and in response to determining that the quantity of the failed memory cells is less than a threshold, ending the read operation.
2. 2 . The method of claim 1 , wherein the threshold is a value that is less than 5% of a quantity of memory cells coupled to the word line.
3. 3 . The method of claim 1 , wherein determining the quantity of the failed memory cells comprises: determining, in latches of a page buffer of the memory device, a quantity of memory cells that are read as “1”.
4. 4 . The method of claim 1 , comprising: in response to determining that the quantity of the failed memory cells is less than the threshold, sending a response indicating that a memory page associated with the word line is a zero page.
5. 5 . The method of claim 4 , wherein the zero page is associated with a word line coupled to a set of memory cells, wherein threshold voltages of the set of memory cells are higher than a threshold level that is higher than a starting read voltage for reading each of a plurality of memory pages of the memory device.
6. 6 . The method of claim 1 , wherein the memory cells are triple-level cells, and wherein the first read voltage is a starting read voltage for reading one of a lower page, a middle page, or an upper page associated with the word line.
7. 7 . The method of claim 1 , wherein the memory cells are quad-level cells, and wherein the first read voltage is a starting read voltage for reading one of a lower page, a middle page, an upper page, or an extra page associated with the word line.
8. 8 . The method of claim 1 , comprising: performing the read operation in response to receiving a specific command indicating to identify zero pages in the memory device.
9. 9 . The method of claim 1 , comprising: performing the read operation in response to: receiving a read command; and determining that an enable bit stored in the memory device indicates the memory device to identify zero pages when performing the read operation.
10. 10 . The method of claim 9 , further comprising: in response to determining that the quantity of failed memory cells is greater than or equal to the threshold, performing the read operation based on a second read voltage on the memory cells, wherein the second read voltage is higher than the first read voltage.
11. 11 . A memory device, comprising: a memory array comprising memory cells coupled to a word line; and a peripheral circuit coupled to the memory array, wherein the peripheral circuit is configured to perform operations comprising: performing, based on a first read voltage, a read operation on memory cells coupled to a word line of the memory device; determining a quantity of failed memory cells, wherein threshold voltages of the failed memory cells are lower than the first read voltage; and in response to determining that the quantity of failed memory cells is less than a threshold, ending the read operation.
12. 12 . The memory device of claim 11 , wherein the threshold is a value that is less than 5% of a quantity of memory cells coupled to the word line.
13. 13 . The memory device of claim 11 , wherein determining the quantity of the failed memory cells comprises: determining, in latches of a page buffer of the memory device, a quantity of memory cells that are read as “1”.
14. 14 . The memory device of claim 11 , wherein the operations comprise: in response to determining that the quantity of the failed memory cells is less than the threshold, sending a response indicating that a memory page associated with the word line is a zero page.
15. 15 . The memory device of claim 14 , wherein the zero page is associated with a word line coupled to a set of memory cells, wherein threshold voltages of the set of memory cells are higher than a threshold level that is higher than a starting read voltage for reading each of a plurality of memory pages of the memory device.
16. 16 . The memory device of claim 11 , wherein the memory cells are triple-level cells, and wherein the first read voltage is a starting read voltage for reading one of a lower page, a middle page, or an upper page associated with the word line.
17. 17 . The memory device of claim 11 , wherein the memory cells are quad-level cells, and wherein the first read voltage is a starting read voltage for reading one of a lower page, a middle page, an upper page, or an extra page associated with the word line.
18. 18 . A memory system, comprising: a memory device comprising memory cells coupled to a word line; and a memory controller coupled to the memory device, wherein the memory device is configured to perform operations comprising: receiving a read command from the memory controller; performing, based on a first read voltage, a read operation on the memory cells; determining a quantity of failed memory cells, wherein the failed memory cells are memory cells having threshold voltages lower than the first read voltage; and in response to a result of the read operation, sending a response to the memory controller, wherein the response indicates that a memory page associated with the word line is a zero page.
19. 19 . The memory system of claim 18 , wherein the operations comprise: determining a quantity of failed memory cells, wherein the failed memory cells are memory cells having threshold voltages lower than the first read voltage, wherein the memory device is configured to send the response to the memory controller in response to determining that the quantity of the failed memory cells is less than a threshold.
20. 20 . The memory system of claim 19 , wherein the operations comprise: in response to determining that the quantity of the failed memory cells is less than the threshold, ending the read operation.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Application No. PCT/CN2024/129641, filed on Nov. 4, 2024, the disclosure of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD This present disclosure generally relates to the field of semiconductor technology, and more particularly, to systems and methods for performing read operations in a memory device. BACKGROUND Flash memory is a low-cost, high-density, nonvolatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed by flash memory, for example, program (write) and erase operations, to change the threshold voltage of each memory cell to a respective level. For NAND flash memory, an erase operation can be performed at the block level, a program operation can be performed at the page level, and a read operation can be performed at the page level. SUMMARY The present disclosure involves methods, apparatuses, and systems for performing read operations in a memory device. One aspect of the present disclosure features an example method for operating a memory device. The method includes performing, based on a first read voltage, a read operation on memory cells coupled to a word line of the memory device; determining a quantity of failed memory cells, the failed memory cells being memory cells having threshold voltages lower than the first read voltage; and in response to determining that the quantity of the failed memory cells is less than a threshold, ending the read operation. In some implementations, the threshold is a value that is less than 5% of a quantity of memory cells coupled to the word line. In some implementations, determining the quantity of the failed memory cells includes determining, in latches of a page buffer of the memory device, a quantity of memory cells that are read as “1”. In some implementations, the method includes, in response to determining that the quantity of the failed memory cells is less than the threshold, sending a response indicating that a memory page associated with the word line is a zero page. In some implementations, the zero page is associated with a word line coupled to a set of memory cells. Threshold voltages of the set of memory cells are higher than a threshold level that is higher than a starting read voltage for reading each of a plurality of memory pages of the memory device. In some implementations, the memory cells are triple-level cells. The first read voltage is a starting read voltage for reading one of a lower page, a middle page, or an upper page associated with the word line. In some implementations, the memory cells are quad-level cells. The first read voltage is a starting read voltage for reading one of a lower page, a middle page, an upper page, or an extra page associated with the word line. In some implementations, the method includes performing the read operation in response to receiving a specific command indicating to identify zero pages in the memory device. In some implementations, the method includes performing the read operation in response to receiving a read command and determining that an enable bit stored in the memory device indicates the memory device to identify zero pages when performing the read operation. In some implementations, the method includes, in response to determining that the quantity of failed memory cells is greater than or equal to the threshold, performing the read operation based on a second read voltage on the memory cells. The second read voltage is higher than the first read voltage. Another aspect of the present disclosure features a memory device. The memory device includes a memory array including memory cells coupled to a word line, and a peripheral circuit coupled to the memory array. The peripheral circuit is configured to perform operations including performing, based on a first read voltage, a read operation on memory cells coupled to a word line of the memory device; determining a quantity of failed memory cells, the failed memory cells being memory cells having threshold voltages lower than the first read voltage; and in response to determining that the quantity of the failed memory cells is less than a threshold, ending the read operation. In some implementations, the threshold is a value that is less than 5% of a quantity of memory cells coupled to the word line. In some implementations, determining the quantity of the failed memory cells includes determining, in latches of a page buffer of the memory device, a quantity of memory cells that are read as “1”. In some implementations, the operations include in response to determining that the quantity of the failed memory cells is less than the threshold, sending a response indicating that a memory page associated with the word line is a zero page. In some implementations, the zero page is associated with a word line