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US-20260126919-A1 - APPARATUS WITH TIME-BASED READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME

US20260126919A1US 20260126919 A1US20260126919 A1US 20260126919A1US-20260126919-A1

Abstract

Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.

Inventors

  • Murong Lang
  • Tingjun Xie
  • FANGFANG ZHU
  • Zhenming Zhou
  • Jiangli Zhu

Assignees

  • MICRON TECHNOLOGY, INC.

Dates

Publication Date
20260507
Application Date
20251231

Claims (20)

  1. 1 . An apparatus, comprising: data storage cells grouped into at least a first group and a second group; and a controller operably coupled to the data storage cells and configured to: determine a delay between programming the first and second groups of data storage cells; and determine, based on the delay, at least one of (1) a first read level for reading from the first group and (2) a second read level, different from the first read level, for reading from the second group.
  2. 2 . The apparatus of claim 1 , wherein: a difference between the first and second read levels corresponds to an imbalance in charge loss between the first and second groupings occurring during the delay; and the first and second groups of the data storage cells correspond to non-overlapping portions of a memory block.
  3. 3 . The apparatus of claim 1 , wherein the controller is configured to: compute one of the first and the second read levels based on adjusting a base read level according to the delay; and compute a remaining one of the first and second read levels as the base read level.
  4. 4 . The apparatus of claim 3 , wherein the controller is configured to dynamically derive the base read level according to one or more real-time characteristics of the data storage cells.
  5. 5 . The apparatus of claim 3 , wherein the controller is configured to: determine a reference threshold voltage within a block of the data storage cells based on applying one or more voltage pulses to the block, wherein the block includes the first and second groups; and dynamically derive the base read level for the memory block based on the reference threshold voltage.
  6. 6 . The apparatus of claim 1 , wherein the controller is configured to determine the first and/or the second read levels when the delay meets or exceeds a minimum threshold.
  7. 7 . The apparatus of claim 1 , wherein the controller is configured to determine the first and second read levels based on identifying an offset between the first and second read levels using a lookup table (LUT).
  8. 8 . The apparatus of claim 7 , wherein the controller is configured to identify the offset based on adjusting the value from the LUT according to (1) the delay, (2) one or more adjacent values corresponding to corresponding discrete time values that surround the delay, (3) a predetermined rounding process for the delay, or a combination thereof.
  9. 9 . The apparatus of claim 7 , wherein the LUT corresponds to at least one of the first and second groups and includes for each group a set of adjustment values that correspond to different discrete delay durations, wherein the set of adjustment values maintain either an increasing pattern or a decreasing pattern (1) as the discrete delay durations increase and/or (2) as the level depth increases.
  10. 10 . The apparatus of claim 1 , wherein the controller is configured to further fine-tune the first and/or the second read levels using a predetermined increment, a set of read operations, or a combination thereof.
  11. 11 . A control circuit configured to control operations of data storage cells, comprising: a clock counter configured to determine a delay between programming a first group of data storage cells and a second group of data storage cells; and a logic circuit coupled to the clock counter and configured to determine, based on the delay, (1) a first read level for reading from the first group of data storage cells and (2) a second read level, different from the second read level, for reading from the second group of data storage cells.
  12. 12 . The control circuit of claim 11 , wherein the logic circuit is configured to: dynamically determine a base read level according to a reference threshold voltage associated with the first and second groups, wherein one of the first and second read levels is determined as the base read level, and wherein another of the first and second read levels is determined based on adjusting the base read level by an offset associated with the delay.
  13. 13 . The control circuit of claim 12 , wherein: the logic circuit is configured to implement write operations to the first group before the second group; and the second read level is computed based the base read level and without adjusting by the offset level.
  14. 14 . The control circuit of claim 12 , wherein the first read level for the first group is computed based on adjusting the base read level by the offset when the delay is greater than a minimum threshold.
  15. 15 . The control circuit of claim 11 , wherein: The first and second groups of the data storage cells correspond to (1) separate decks and (2) a single memory block; the logic circuit is configured to separately write to the first and second groups; and the first and second read levels are computed separately for the same memory block.
  16. 16 . A method of operating memory cells arranged into at least a first group and a second group, the method comprising: determining a delay that represents a duration between programming the first and second groups; and based on the delay, determine at least one of (1) a first read level for reading from the first group and (2) a second read level, different from the first read level, for reading from the second group.
  17. 17 . The method of claim 16 , further comprising: dynamically determining a base read level according to a real-time condition or a history thereof for the, wherein one of the first and second read levels are computed by adjusting the base read level by an offset and other of the first and second read levels corresponds to the base read level, wherein the offset corresponds to the delay.
  18. 18 . The method of claim 17 , wherein the offset is identified using a lookup table (LUT).
  19. 19 . The method of claim 16 , wherein: the first and second groups both correspond to a same block of memory cells; the determined delay represents the duration between a programming of the first group and a subsequent programming of the second group; and dynamically computing the first read level by decreasing a base read level by the offset for reading from the first deck.
  20. 20 . The method of claim 19 , further comprising: determining that the delay satisfies a minimum threshold, wherein the first read level is adjusted when the deck separation delay satisfies the minimum threshold.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application is a continuation of Ser. No. 18/610,770, filed Mar. 20, 2024, which is a continuation of U.S. patent application Ser. No. 17/938,307, filed Oct. 5, 2022, now U.S. Pat. No. 11,966,591, which claims benefit of U.S. Provisional Application No. 63/347,876, filed Jun. 1, 2022; the subject matter thereof is incorporated herein by reference thereto. This application also contains subject matter related to a concurrently-filed U.S. Patent Application by Murong Lang, Tingjun Xie, Fangfang Zhu, Jiangli Zhu, and Zhenming Zhou titled “APPARATUS WITH MULTI-DECK READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME.” The related application is assigned to Micron Technology, Inc., and is identified by U.S. patent application Ser. No. 17/938,153 filed Oct. 5, 2022. TECHNICAL FIELD The disclosed embodiments relate to devices, and, in particular, to semiconductor memory devices with read level management and methods for operating the same. BACKGROUND Memory systems can employ memory devices to store and access information. The memory devices can include volatile memory devices, non-volatile memory devices (e.g., flash memory employing “NAND” technology or logic gates, “NOR” technology or logic gates, or a combination thereof), or a combination device. The memory devices utilize electrical energy, along with corresponding threshold levels or processing/reading voltage levels, to store and access data. However, the performance or characteristics of the memory devices change or degrade over time or usage. The change in performance or characteristics conflicts with the threshold or processing voltage levels over time, leading to errors and other performance issues. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects, features, and advantages of the disclosure will be apparent from the following description of embodiments as illustrated in the accompanying drawings, in which reference characters refer to the same parts throughout the various views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating principles of the disclosure. FIG. 1 is a block diagram of a computing system in accordance with an embodiment of the present technology. FIG. 2 is an illustration of a three-dimensional (3D) memory architecture in accordance with an embodiment of the present technology. FIG. 3A is an illustration of changes in stored charge levels associated with delayed and unbalanced operations. FIG. 3B is an illustration of errors associated with the delayed and unbalanced operations. FIG. 4 is an illustration of an example offset table in accordance with an embodiment of the present technology. FIG. 5 is a flow diagram illustrating an example method of operating an apparatus in accordance with an embodiment of the present technology. FIG. 6 is a schematic view of a system that includes an apparatus in accordance with an embodiment of the present technology. DETAILED DESCRIPTION As described in greater detail below, the technology disclosed herein relates to an apparatus, such as memory systems, systems with memory devices, related methods, etc., for managing read levels/voltages. A computing system, such as an enterprise computer, a server, a distributed computing system, or the like, may include a memory device configured to store data into different portions at different times. As an illustrative example, the computing system can include the memory system having a three-dimensional (3D) NAND architecture. Such memory system can have memory cells organized in multiple layers. In some embodiments, word-lines used to access the memory cells can be arranged parallel to the layers (e.g., extending laterally) and bit lines can be arranged orthogonal to the orientation of the layers (e.g., extending vertically). The layers can be grouped into decks (groupings of, e.g., 48, 88, or 96 word lines), which may be written to at different times. For example, the memory system may have the memory cells arranged in two groupings (e.g., an upper deck and a lower deck). For one block of memory, half of the cells in one grouping (e.g., the lower deck) may be programmed before other groupings (e.g., the upper deck). The targeted memory block may remain open until the remaining groupings are programmed, such as after a delay. As the programming delay increases, the differences in the stored charges of the different decks can also increase, which can cause imbalances in reading the stored data. For example, for a given read voltage, the initially programmed cells (e.g., the lower deck) may produce higher error rates than the subsequently programmed cells. To improve the balance across the different groupings of memory cells, embodiments of the technology described herein may include a time-based read level management mechanism that controls or dynamically adjusts the read levels for the different groupings according to a deck separation delay. The memo