US-20260126921-A1 - METHODS AND APPARATUSES FOR OPERATING MEMORY SYSTEMS

Abstract

Methods, devices, apparatuses, and systems for operating memory systems are provided. In one aspect, a memory system includes a memory device including a plurality of memory blocks, and a memory controller coupled to the memory device. The memory controller is configured to identify a first memory block of the plurality of memory blocks, where the first memory block includes specific data that is invalid. The memory controller can be configured to increase a priority level of the first memory block among the plurality of memory blocks, and perform garbage collection on the memory device based on priority levels of the plurality of memory blocks.

Inventors

• Hao He
• Hua Tan

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260507

Application Date

20250116

Claims (20)

1. 1 . A memory system, comprising: a memory device comprising a plurality of memory blocks; and a memory controller coupled to the memory device, wherein the memory controller is configured to: identify a first memory block of the plurality of memory blocks, wherein the first memory block comprises specific data that is invalid; increase a priority level of the first memory block among the plurality of memory blocks; and perform garbage collection on the memory device based on priority levels of the plurality of memory blocks.
2. 2 . The memory system of claim 1 , wherein the specific data comprises replay-protected-memory-block (RPMB) data.
3. 3 . The memory system of claim 1 , wherein the specific data becomes invalid when new data is written to a same logical address as the specific data.
4. 4 . The memory system of claim 1 , wherein the memory controller is configured to: identify the first memory block by checking an indication bit corresponding to the first memory block, wherein the indication bit indicates whether the first memory block comprises the specific data that is invalid.
5. 5 . The memory system of claim 1 , wherein the memory controller is configured to: increase the priority level of the first memory block by decreasing a first valid page count (VPC) of the first memory block; and perform a first garbage collection operation on the first memory block before a second memory block having a second VPC that is greater than the first VPC.
6. 6 . The memory system of claim 1 , wherein the memory controller is configured to: receive a purge command to erase invalid specific data in the memory device; and send a response indicating that the invalid specific data in the memory device have been erased.
7. 7 . The memory system of claim 6 , wherein the memory controller is configured to: erase the invalid specific data in a corresponding memory block during the garbage collection before receiving the purge command.
8. 8 . The memory system of claim 1 , wherein the memory controller is configured to: perform the garbage collection on the memory device while the memory device is idle.
9. 9 . The memory system of claim 1 , wherein the memory controller is configured to: perform a first garage collection operation on the first memory block by sending one or more commands to migrate valid data from the first memory block to a target memory block of the memory device and erase the first memory block.
10. 10 . A memory controller, comprising: a processor; and a first interface configured to be coupled to a memory device, wherein the processor is configured to perform garbage collection on the memory device based on priority levels of a plurality of memory blocks in the memory device, and wherein the first interface is configured to: send one or more read commands to read valid data from a first memory block of the plurality of memory blocks, wherein the first memory block comprises specific data that is invalid, and wherein, among the plurality of memory blocks, the first memory block has an increased priority level based on the first memory block comprising the specific data that is invalid; and send one or more write commands to write the valid data read from the first memory block to a target memory block of the memory device.
11. 11 . The memory controller of claim 10 , wherein the processor is configured to: identify the first memory block from the plurality of memory blocks; and increase a priority level of the first memory block among the plurality of memory blocks.
12. 12 . The memory controller of claim 11 , wherein the processor is configured to: increase the priority level of the first memory block by decreasing a first valid page count (VPC) of the first memory block; and perform a first garbage collection operation on the first memory block before a second memory block having a second VPC that is greater than the first VPC.
13. 13 . The memory controller of claim 10 , wherein the memory controller comprises a second interface coupled to a host, wherein the second interface is configured to: receive a purge command to erase invalid specific data in the memory device; and send a response indicating that the invalid specific data in the memory device have been erased.
14. 14 . The memory controller of claim 13 , wherein the processor is configured to erase the invalid specific data in a corresponding memory block during the garbage collection before receiving the purge command.
15. 15 . The memory controller of claim 10 , wherein the processor is configured to perform the garbage collection on the memory device while the memory device is idle.
16. 16 . The memory controller of claim 10 , wherein the specific data comprises replay-protected-memory-block (RPMB) data.
17. 17 . The memory controller of claim 10 , wherein the specific data becomes invalid when new data is written to a same logic address as the specific data.
18. 18 . The memory controller of claim 10 , wherein the processor is configured to: identify the first memory block by checking an indication bit corresponding to the first memory block, wherein the indication bit indicates whether the first memory block comprises the specific data that is invalid.
19. 19 . The memory controller of claim 10 , wherein the processor is configured to: perform a first garage collection operation on the first memory block by sending one or more commands to migrate valid data from the first memory block to a target memory block of the memory device and erase the first memory block.
20. 20 . A method of operating a memory system, comprising: identifying a first memory block of a plurality of memory blocks of a memory device of the memory system, wherein the first memory block comprises specific data that is invalid; increasing a priority level of the first memory block among the plurality of memory blocks; and performing garbage collection on the memory device based on priority levels of the plurality of memory blocks.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Application No. PCT/CN2024/129625, filed on Nov. 4, 2024, the disclosure of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD The present disclosure generally relates to memory devices and memory systems, and in particular, to operating memory systems. BACKGROUND Flash memory is a low-cost, high-density, nonvolatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed by a flash memory, for example, program (write) or read operations. Operations performed by a flash memory can affect temperature of the flash memory. SUMMARY The present disclosure involves methods, apparatuses, and systems for operating a memory system, e.g., managing purge commands in the memory system. One aspect of the present disclosure provides a memory device including a plurality of memory blocks, and a memory controller coupled to the memory device. The memory controller is configured to identify a first memory block of the plurality of memory blocks, where the first memory block includes specific data that is invalid. The memory controller is further configured to increase a priority level of the first memory block among the plurality of memory blocks, and perform garbage collection on the memory device based on priority levels of the plurality of memory blocks. In some implementations, the specific data includes replay-protected-memory-block (RPMB) data. In some implementations, the specific data becomes invalid when new data is written to a same logical address as the specific data. In some implementations, the memory controller is configured to identify the first memory block by checking an indication bit corresponding to the first memory block. The indication bit indicates whether the first memory block includes the specific data that is invalid. In some implementations, the memory controller is configured to increase the priority level of the first memory block by decreasing a first valid page count (VPC) of the first memory block, and perform a first garbage collection operation on the first memory block before a second memory block having a second VPC that is greater than the first VPC. In some implementations, the memory controller is configured to receive a purge command to erase invalid specific data in the memory device, and send a response indicating that the invalid specific data in the memory device has been erased. In some implementations, the memory controller is configured to erase the invalid specific data in a corresponding memory block during the garbage collection before receiving the purge command. In some implementations, the memory controller is configured to perform the garbage collection on the memory device while the memory device is idle. In some implementations, the memory controller is configured to perform a first garage collection operation on the first memory block by sending one or more commands to migrate valid data from the first memory block to a target memory block of the memory device and erase the first memory block. Another aspect of the present disclosure features a memory controller. The memory controller includes a processor, and a first interface coupled to a memory device. The processor is configured to perform garbage collection on the memory device based on priority levels of a plurality of memory blocks in the memory device. The first interface is configured to send one or more read commands to read valid data from a first memory block of the plurality of memory blocks. The first memory block includes specific data that is invalid. Among the plurality of memory blocks, the first memory block has an increased priority level based on the first memory block including the specific data that is invalid. The first interface is further configured to send one or more write commands to write the valid data read from the first memory block to a target memory block of the memory device. In some implementations, the processor is configured to identify the first memory block from the plurality of memory blocks, and increase a priority level of the first memory block among the plurality of memory blocks. In some implementations, the processor is configured to increase the priority level of the first memory block by decreasing a first valid page count (VPC) of the first memory block, and perform a first garbage collection operation on the first memory block before a second memory block having a second VPC that is greater than the first VPC. In some implementations, the memory controller includes a second interface coupled to a host. The second interface is configured to receive a purge command to erase invalid specific data in the memory device, and send a response indicating that the invalid specific data in the memory device have been erased. In some implementati