US-20260126924-A1 - COMPLETE AND INCOMPLETE SUPERBLOCK GENERATION

US20260126924A1US 20260126924 A1US20260126924 A1US 20260126924A1US-20260126924-A1

Abstract

Methods, systems, and devices for complete and incomplete superblock generation are described. A memory system may be configured to generate and access complete and incomplete superblocks by replacing invalid physical blocks with valid physical blocks from a same plane. For example, he memory system may perform a scan to determine (e.g., identify) which blocks are valid, invalid, or both. The memory system may replace invalid blocks from superblocks having a relatively small quantity of invalid blocks with blocks (e.g., blocks from a same plane) from superblocks having a relatively large quantity of invalid blocks, which may result in the generation of complete and incomplete superblocks.

Inventors

Mingyi Li
Xiaolai Zhu
Xing Wang
Xiangang Luo

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260507
Application Date: 20230314

Claims (20)

1 . An apparatus, comprising: a memory device comprising a plurality of superblocks; and a controller coupled with the memory device and configured to cause the apparatus to: determine whether a first superblock comprises a first physical block of a first type and a second physical block of a first type, wherein the first superblock comprises a plurality of physical blocks that are each associated with a respective plane of the memory device; determine whether a second superblock comprises a third physical block of a second type based at least in part on determining that the first superblock comprises the first physical block of the first type and the second physical block of the first type; replace the first physical block with the third physical block based at least in part on determining that the second superblock comprises the third physical block of the second type; and access one or more physical blocks associated with the first superblock based at least in part on replacing the first physical block with the third physical block.
2 . The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: determine that a third superblock comprises a fourth physical block of the first type before determining that the first superblock comprises the first physical block and the second physical block of the first type; determine that a fourth superblock comprises a fifth physical block of the second type based at least in part on determining that the third superblock comprises the fourth physical block of the first type; and replace the fourth physical block with the fifth physical block based at least in part on determining that the fourth superblock comprises the fifth physical block of the second type.
3 . The apparatus of claim 2 , wherein: the first superblock comprises an incomplete superblock based at least in part on replacing the first physical block with the third physical block; and the third superblock comprises a complete superblock based at least in part on replacing the fourth physical block with the fifth physical block.
4 . The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: determine that the first physical block and the third physical block are associated with a same plane of the memory device; and replace the first physical block with the third physical block based at least in part on determining that the first physical block and the third physical block are associated with the same plane of the memory device.
5 . The apparatus of claim 4 , wherein the controller is further configured to cause the apparatus to: determine that a plurality of superblocks associated with the memory device do not include a physical block of the second type associated with a same plane as the second physical block based at least in part on replacing the first physical block with the third physical block; and refrain from replacing the second physical block based at least in part on determining that the plurality of superblocks associated with the memory device do not include a physical block of the second type associated with a same plane as the second physical block.
6 . The apparatus of claim 4 , wherein the controller is further configured to cause the apparatus to: designating a first plane as a plane of the first type based at least in part on replacing the first physical block with the third physical block, wherein the second physical block is associated with the first plane; and refraining from replacing the second physical block based at least in part on designating the first plane as a plane of the first type.
7 . The apparatus of claim 1 , wherein replacing the first physical block with the third physical block is configured to cause the apparatus to: update a mapping between the first physical block with a physical block address associated with the third physical block.
8 . The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: receive an access command associated with the first physical block based at least in part on replacing the first physical block with the third physical block, the access command comprising a first virtual address; and determine whether the first virtual address satisfies a threshold value based at least in part on receiving the access command.
9 . The apparatus of claim 8 , wherein the controller is further configured to cause the apparatus to: access a first physical block address of the memory device based at least in part on determining that the first virtual address satisfies the threshold value.
10 . The apparatus of claim 8 , wherein the controller is further configured to cause the apparatus to: access a second physical block address of the memory device based at least in part on determining that the first virtual address does not satisfy the threshold value.
11 . The apparatus of claim 1 , wherein: physical blocks of the first type comprise invalid physical blocks and physical blocks of the second type comprise valid physical blocks.
12 . The apparatus of claim 1 , wherein the first superblock comprises a plurality of physical blocks of the second type and the second superblock comprises a plurality of physical blocks of the first type.
13 . The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: determine that a fifth superblock comprises a sixth physical block, a seventh physical block, and an eighth physical block of the first type based at least in part on replacing the first physical block with the third physical block; determine that a sixth superblock comprises at least a ninth physical block of the second type based at least in part on determining that the fifth superblock comprises the sixth physical block, the seventh physical block, and the eighth physical block of the first type; and replace the eighth physical block with the ninth physical block based at least in part on determining that the sixth superblock comprises the ninth physical block of the second type.
14 . The apparatus of claim 13 , wherein the controller is further configured to cause the apparatus to: determine that a seventh superblock comprises at least a tenth physical block of the second type based at least in part on replacing the eighth physical block with the ninth physical block; and replace the seventh physical block with the tenth physical block based at least in part on determining that the seventh superblock comprises the tenth physical block of the second type, wherein the fifth superblock comprises an incomplete superblock based at least in part on replacing the seventh physical block with the tenth physical block.
15 . The apparatus of claim 1 , wherein the controller is further configured to cause the apparatus to: scan a plurality of superblocks associated with the memory device to identify physical blocks of the first type and of the second type, wherein determining that the first superblock comprises the first physical block and the second physical block of the first type is based at least in part on scanning the plurality of superblocks.
16 . The apparatus of claim 15 , wherein the controller is further configured to cause the apparatus to: assign each superblock of the plurality of superblocks to one or more slots associated with the memory device based at least in part on scanning the plurality of superblocks, wherein each slot of the one or more slots is associated with superblocks having a respective quantity of physical blocks of the first type.
17 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to: determine whether a first superblock comprises a first physical block of a first type and a second physical block of a first type, wherein the first superblock comprises a plurality of physical blocks that are each associated with a respective plane of a memory device; determine whether a second superblock comprises a third physical block of a second type based at least in part on determining that the first superblock comprises the first physical block of the first type and the second physical block of the first type; replace the first physical block with the third physical block based at least in part on determining that the second superblock comprises the third physical block of the second type; and access one or more physical blocks associated with the first superblock based at least in part on replacing the first physical block with the third physical block.
18 . The non-transitory computer-readable medium of claim 17 , wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: determine that a third superblock comprises a fourth physical block of the first type before determining that the first superblock comprises the first physical block and the second physical block of the first type; determine that a fourth superblock comprises a fifth physical block of the second type based at least in part on determining that the third superblock comprises the fourth physical block of the first type; and replace the fourth physical block with the fifth physical block based at least in part on determining that the fourth superblock comprises the fifth physical block of the second type.
19 . The non-transitory computer-readable medium of claim 18 , wherein: the first superblock comprises an incomplete superblock based at least in part on replacing the first physical block with the third physical block; and the third superblock comprises a complete superblock based at least in part on replacing the fourth physical block with the fifth physical block.
20 . A method, comprising: determining whether a first superblock comprises a first physical block of a first type and a second physical block of a first type, wherein the first superblock comprises a plurality of physical blocks that are each associated with a respective plane of a memory device; determining whether a second superblock comprises a third physical block of a second type based at least in part on determining that the first superblock comprises the first physical block of the first type and the second physical block of the first type; replacing the first physical block with the third physical block based at least in part on determining that the second superblock comprises the third physical block of the second type; and accessing one or more physical blocks associated with the first superblock based at least in part on replacing the first physical block with the third physical block.

Description

CROSS REFERENCE The present Application for Patent is a 371 national phase filing of International Patent Application No. PCT/CN2023/081274 by Li et al., entitled “COMPLETE AND INCOMPLETE SUPERBLOCK GENERATION,” filed Mar. 14, 2023, assigned to the assignee hereof, and expressly incorporated by reference in its entirety herein. TECHNICAL FIELD The following relates to one or more systems for memory, including complete and incomplete superblock generation. BACKGROUND Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign) states to the memory cells. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of a system that supports complete and incomplete superblock generation in accordance with examples as disclosed herein. FIG. 2 illustrates an example of a block diagram that supports complete and incomplete superblock generation in accordance with examples as disclosed herein. FIG. 3 illustrates an example of a process flow that supports complete and incomplete superblock generation in accordance with examples as disclosed herein. FIG. 4 illustrates an example of a process flow that supports complete and incomplete superblock generation in accordance with examples as disclosed herein. FIG. 5 illustrates an example of a process flow that supports complete and incomplete superblock generation in accordance with examples as disclosed herein. FIG. 6 illustrates a block diagram of a memory system that supports complete and incomplete superblock generation in accordance with examples as disclosed herein. FIG. 7 illustrates a flowchart showing a method or methods that support complete and incomplete superblock generation in accordance with examples as disclosed herein. DETAILED DESCRIPTION A memory system may support the use of superblocks, which include blocks (e.g., a set of blocks) from a contiguous set of planes (e.g., each plane) of the memory system. In some cases, the memory system may perform access operations on the blocks of the superblock. In some instances, however, the memory system may be unable to perform one or more access operations on the superblock if one or more blocks of the set of blocks associated with the superblock are invalid (e.g., bad, corrupt, otherwise inaccessible). In some such cases, the memory system may attempt to replace the one or more invalid blocks with one or more valid blocks from a replacement pool of blocks. However, such pools of replacement blocks may increase overprovisioning associated with the memory device, which may increase the memory device's overall size. Moreover, such pools of replacement blocks may be relatively ineffective in replacing invalid blocks, which may decrease the usable storage capacity of the memory system. Accordingly, a memory system configured to generate complete and incomplete, usable superblocks may be desirable. In accordance with examples as described herein, a memory system may be configured to generate and access complete superblocks (e.g., superblocks that do not include invalid blocks) and incomplete superblocks (e.g., superblocks that each include a singular invalid block). For example, the memory system may scan one or more physical blocks associated with one or more superblocks to determine which physical blocks are invalid and/or valid. The superblocks may then be assigned to slots, where each slot may include one or more superblocks each with a respective quantity of invalid blocks (e.g., slot 0 includes superblocks with 0 invalid blocks, slot 1 includes superblocks 1 with 1 invalid block). The