US-20260126926-A1 - MEMORY DEVICE WITH NEAR-MEMORY PROCESSING UNIT AND MEMORY MANAGEMENT

US20260126926A1US 20260126926 A1US20260126926 A1US 20260126926A1US-20260126926-A1

Abstract

A memory device includes: a memory storing instructions; and a processing unit including one or more processors, wherein the memory device is connected with a host processor through an interface, and wherein, the instructions, when executed by the processing unit, cause the memory device to: select, from among memory blocks stored in the memory, candidate hot memory blocks, the selecting based on access counts of the respective memory blocks stored in the memory; select a hot sub-block based on a number access counts of respective sub-blocks, including the hot sub-block, split from the selected candidate hot memory blocks; and transmit the selected hot sub-block to the host processor, based on a memory command regarding the hot sub-block, wherein the memory command is received from the host processor by the processing unit.

Inventors

Maksim OSTAPENKO
Deok Jae OH
JIHOON NAM

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251104
Priority Date: 20241104

Claims (20)

1 . A memory device comprising: a memory storing instructions; and a processing unit comprising one or more processors, wherein the memory device is connected with a host processor through an interface, and wherein, the instructions, when executed by the processing unit, cause the memory device to: select, from among memory blocks stored in the memory, candidate hot memory blocks, the selecting based on access counts of the respective memory blocks stored in the memory; select a hot sub-block based on a number access counts of respective sub-blocks, including the hot sub-block, split from the selected candidate hot memory blocks; and transmit the selected hot sub-block to the host processor, based on a memory command regarding the hot sub-block, wherein the memory command is received from the host processor by the processing unit.
2 . The memory device of claim 1 , wherein, the instructions, when executed by the processing unit, cause the memory device to: select, as the candidate hot memory blocks, those of the memory blocks having access counts greater than a first access count threshold; split each of the selected candidate hot memory blocks into the sub-blocks; and select, the hot sub-block, from among the split sub-blocks, based on the hot sub-block having an access count that is greater than a second access count threshold.
3 . The memory device of claim 1 , wherein, the instructions, when executed by the processing unit, cause the memory device to: determine the access counts of the respective memory blocks during a first time range; and determine the access counts each of the respective sub-blocks during a second time range that at least partially follows the first time range.
4 . The memory device of claim 3 , wherein the first access count threshold is determined based on a ratio of a time length of the first time range to a time length of a period comprising the first time range and the second time range.
5 . The memory device of claim 1 , wherein a block size of the memory blocks is larger than a block size of the sub-blocks.
6 . The memory device of claim 1 , wherein the memory further comprises a hot buffer, wherein, the instructions, when executed by the processing unit, cause the memory device to: store an address of the selected hot sub-block in the hot buffer; receive a read command for the hot sub-block, based on the host processor accessing the hot buffer; and execute the read command by transmitting the hot sub-block to the host processor, wherein the hot sub-block in the memory is deallocated by the host processor after being transmitted to the host processor.
7 . The memory device of claim 6 , wherein the host processor is configured to access the hot buffer of the memory device using memory-mapped input/output (MMIO).
8 . The memory device of claim 6 , wherein, the instructions, when executed by the processing unit, cause the memory device to delete the address of the selected hot sub-block from in the hot buffer after the hot sub-block is transmitted to the host processor.
9 . The memory device of claim 1 , wherein the memory device comprises a secondary memory device, and the hot sub-block is stored in a main memory device of the host processor after information about the hot sub-block is transmitted to the host processor.
10 . The memory device of claim 1 , wherein the memory comprises a first memory zone and a second memory zone, wherein, the instructions, when executed by the processing unit, cause the memory device to: merge, into a superblock, among those of the memory blocks which are stored in the first memory zone, memory blocks having respective access counts that are less than an access count threshold; configure the merged superblock as the second memory zone; and limit counting a number of times accessing the merged superblock.
11 . The memory device of claim 1 , wherein the memory comprises a first memory zone and a second memory zone, wherein, the instructions, when executed by the processing unit, cause the memory device to: based on an access to a superblock stored in the second memory zone, obtain some of the memory blocks by splitting the accessed superblock thereinto; configure the splitted memory blocks as the first memory zone; and count a number of times accessing the splitted memory blocks.
12 . A method, performed by a memory device, of managing a memory in the memory device, the method comprising: selecting, from among memory blocks stored in the memory of the memory device, candidate hot memory blocks, the selecting based on access counts of the respective memory blocks stored in the memory of the memory device; selecting a hot sub-block based on access counts of respective sub-blocks, including the hot sub-block, split from the selected candidate hot memory blocks; and transmitting the selected hot sub-block to a host processor, based on a memory command regarding the hot sub-block, wherein the memory command is received from the host processor by the memory device.
13 . The method of claim 12 , wherein the candidate hot memory blocks are selected based on having respective access counts greater than a first access count threshold, and the selecting of the hot sub-block comprises: splitting each of the selected candidate hot memory blocks into the sub-blocks; and selecting, as the hot sub-block, from among the split sub-blocks, a sub-block having an access count that is greater than or equal to a second access count threshold.
14 . The method of claim 12 , wherein the selecting of the candidate hot memory blocks comprises determining the access counts of the memory blocks during a first time range, and the selecting of the hot sub-block comprises determining access counts each of the respective sub-blocks during a second time range that at least partially follows the first time range.
15 . The method of claim 12 , further comprising: storing an address of the selected hot sub-block in a hot buffer of the memory device, wherein the transmitting of the hot sub-block to the host processor comprises: receiving a read command for the hot sub-block, based on the host processor accessing the hot buffer; and transmitting the hot sub-block to the host processor, based on the read command, wherein the hot sub-block in the memory is deallocated by the host processor after being transmitted to the host processor.
16 . The method of claim 15 , further comprising: deleting the address of the selected hot sub-block, which is stored in the hot buffer, after the hot sub-block is transmitted to the host processor.
17 . The method of claim 12 , wherein the memory device comprises a secondary memory device, and the hot sub-block is stored in a main memory device of the host processor after information about the hot sub-block is transmitted to the host processor.
18 . The method of claim 12 , wherein the memory of the memory device comprises a first memory zone and a second memory zone, wherein the method further comprises: merging, into a superblock, among those of the memory blocks which are stored in the first memory zone, memory blocks having respective access counts that are less than an access count threshold; configuring the merged superblock as the second memory zone; and limiting counting a number of times accessing the merged superblock.
19 . The method of claim 12 , wherein the memory of the memory device comprises a first memory zone and a second memory zone, wherein the method further comprises: based on an occurrence of access to a superblock stored in the second memory zone, obtaining memory blocks by splitting the accessed superblock; configuring the memory blocks obtained through the split as the first memory zone; and counting a number of times accessing the memory blocks obtained through the split.
20 . A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 12 .

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit under 35 USC § 119(a) of Korean Patent Application No. 10-2024-0154361, filed on Nov. 4, 2024, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. BACKGROUND 1. Field The following description relates to a memory device with a near-memory processing unit and with technology for managing a memory. 2. Description of Related Art In a large-scale computing environment, high-speed dynamic random-access memory (DRAM) increasingly dominates infrastructure spending, and this trend will only get worse without architectural improvement. Deployed memory costs may be reduced by replacing a portion of existing DRAM with a slower but cheaper memory media and establishing a tiered memory system in which two tiers are transparently directly addressable and cacheable as one memory space. SUMMARY This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. In one general aspect, a memory device includes: a memory storing instructions; and a processing unit including one or more processors, wherein the memory device is connected with a host processor through an interface, and wherein, the instructions, when executed by the processing unit, cause the memory device to: select, from among memory blocks stored in the memory, candidate hot memory blocks, the selecting based on access counts of the respective memory blocks stored in the memory; select a hot sub-block based on a number access counts of respective sub-blocks, including the hot sub-block, split from the selected candidate hot memory blocks; and transmit the selected hot sub-block to the host processor, based on a memory command regarding the hot sub-block, wherein the memory command is received from the host processor by the processing unit. The instructions, when executed by the processing unit, may cause the memory device to: select, as the candidate hot memory blocks, those of the memory blocks having access counts greater than a first access count threshold; split each of the selected candidate hot memory blocks into the sub-blocks; and select, the hot sub-block, from among the split sub-blocks, based on the hot sub-block having an access count that is greater than a second access count threshold. The instructions, when executed by the processing unit, may cause the memory device to: determine the access counts of the respective memory blocks during a first time range; and determine the access counts each of the respective sub-blocks during a second time range that at least partially follows the first time range. The first access count threshold may be determined based on a ratio of a time length of the first time range to a time length of a period including the first time range and the second time range. A block size of the memory blocks may be larger than a block size of the sub-blocks. The memory further may further include a hot buffer, wherein, the instructions, when executed by the processing unit, may cause the memory device to: store an address of the selected hot sub-block in the hot buffer; receive a read command for the hot sub-block, based on the host processor accessing the hot buffer; and execute the read command by transmitting the hot sub-block to the host processor, wherein the hot sub-block in the memory is deallocated by the host processor after being transmitted to the host processor. The host processor may be configured to access the hot buffer of the memory device using memory-mapped input/output (MMIO). The instructions, when executed by the processing unit, may cause the memory device to delete the address of the selected hot sub-block from in the hot buffer after the hot sub-block is transmitted to the host processor. The memory device may include a secondary memory device, and the hot sub-block may be stored in a main memory device of the host processor after information about the hot sub-block is transmitted to the host processor. The memory may include a first memory zone and a second memory zone, wherein, the instructions, when executed by the processing unit, may cause the memory device to: merge, into a superblock, among those of the memory blocks which are stored in the first memory zone, memory blocks having respective access counts that are less than an access count threshold; configure the merged superblock as the second memory zone; and limit counting a number of times accessing the merged superblock. The memory may include a first memory zone and a second memory zone, wherein, the instructions, when executed by the processing unit, may cause the memory device to: based on an access to a superbloc