US-20260126929-A1 - RESEQUENCING DATA PROGRAMMED TO MULTIPLE LEVEL MEMORY CELLS AT A MEMORY SUB-SYSTEM

Abstract

An example method includes the operations of: programming a first set of host data items to first memory pages residing at a first region of a memory sub-system; programming a second set of host data items to second memory pages residing at the first region; copying one or more of the first set of host data items to a second region of the memory sub-system, wherein the second region is configured for lower memory pages; and copying one or more of the second set of host data items to a third region of the memory sub-system, wherein the third region is configured for higher memory pages, and wherein a second sequence of the one or more of the first set of host data items at the second region and the one or more of the second set of host data items at the third region correspond to a target sequence.

Inventors

• Kishore Kumar Muchherla
• Ashutosh Malshe
• Peter Feeley
• Jonathan S. Parry
• Akira Goda
• Jeffrey S. McNeil

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260507

Application Date

20260105

Claims (20)

1. 1 . A method, comprising: programming a first set of host data items to first memory pages residing at a first region of a memory sub-system; programming a second set of host data items to second memory pages residing at the first region; copying one or more of the first set of host data items from one or more first memory pages to a second region of the memory sub-system, wherein the second region is configured for lower memory pages, wherein the lower memory pages are programmed using a first programming voltage; and copying one or more of the second set of host data items from one or more second memory pages to a third region of the memory sub-system, wherein the third region is configured for higher memory pages, wherein the higher memory pages are programmed using a second programming voltage that is higher than the first programming voltage, and wherein a second sequence of the copied one or more of the first set of host data items at the second region and the copied one or more of the second set of host data items at the third region correspond to a target sequence.
2. 2 . The method of claim 1 , wherein the target sequence minimizes data fragmentation of host data across one or more memory devices of the memory sub-system.
3. 3 . The method of claim 1 , wherein at least one of the one or more of the first set of host data items or the one or more of the second set of host data items are copied from the first region responsive to detecting an idle time period associated with incoming host data traffic.
4. 4 . The method of claim 1 , wherein the first region of the memory sub-system and the second region of the memory sub-system correspond to regions associated with storing data items that are subject to a media management operation.
5. 5 . The method of claim 1 , wherein the first memory pages correspond to a first memory page level of a first set of memory cells residing at the first region and the second memory pages to one or more second memory page levels of the first set of memory cells.
6. 6 . The method of claim 5 , wherein the second memory pages correspond to at least one of upper memory pages or extra memory pages residing at the first region.
7. 7 . The method of claim 1 , wherein the first region, the second region, and the third region of the memory sub-system each include at least one of a multi-level memory cell, a triple-level memory cell, or a quad-level memory cell.
8. 8 . A system comprising: one or more memory devices; and a processing device coupled to the one or more memory devices, wherein the processing device is to perform operations comprising: programming a first set of host data items to first memory pages residing at a first region of a memory sub-system; programming a second set of host data items to second memory pages residing at the first region; copying one or more of the first set of host data items from one or more first memory pages to a second region of the memory sub-system, wherein the second region is configured for lower memory pages, wherein the lower memory pages are programmed using a first programming voltage; and copying one or more of the second set of host data items from one or more second memory pages to a third region of the memory sub-system, wherein the third region is configured for higher memory pages, wherein the higher memory pages are programmed using a second programming voltage that is higher than the first programming voltage, and wherein a second sequence of the copied one or more of the first set of host data items at the second region and the copied one or more of the second set of host data items at the third region correspond to a target sequence.
9. 9 . The system of claim 8 , wherein the target sequence minimizes data fragmentation of host data across one or more memory devices of the memory sub-system.
10. 10 . The system of claim 8 , wherein at least one of the one or more of the first set of host data items or the one or more of the second set of host data items are copied from the first region responsive to detecting an idle time period associated with incoming host data traffic.
11. 11 . The system of claim 8 , wherein the first region of the memory sub-system and the second region of the memory sub-system correspond to regions associated with storing data items that are subject to a media management operation.
12. 12 . The system of claim 8 , wherein the first memory pages correspond to a first memory page level of a first set of memory cells residing at the first region and the second memory pages to one or more second memory page levels of the first set of memory cells.
13. 13 . The system of claim 12 , wherein the second memory pages correspond to at least one of upper memory pages or extra memory pages residing at the first region.
14. 14 . The system of claim 8 , wherein the first region, the second region, and the third region of the memory sub-system each include at least one of a multi-level memory cell, a triple-level memory cell, or a quad-level memory cell.
15. 15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: programming a first set of host data items to first memory pages residing at a first region of a memory sub-system; programming a second set of host data items to second memory pages residing at the first region; copying one or more of the first set of host data items from one or more first memory pages to a second region of the memory sub-system, wherein the second region is configured for lower memory pages, wherein the lower memory pages are programmed using a first programming voltage; and copying one or more of the second set of host data items from one or more second memory pages to a third region of the memory sub-system, wherein the third region is configured for higher memory pages, wherein the higher memory pages are programmed using a second programming voltage that is higher than the first programming voltage, and wherein a second sequence of the copied one or more of the first set of host data items at the second region and the copied one or more of the second set of host data items at the third region correspond to a target sequence.
16. 16 . The non-transitory computer-readable storage medium of claim 15 , wherein the target sequence minimizes data fragmentation of host data across one or more memory devices of the memory sub-system.
17. 17 . The non-transitory computer-readable storage medium of claim 15 , wherein at least one of the one or more of the first set of host data items or the one or more of the second set of host data items are copied from the first region responsive to detecting an idle time period associated with incoming host data traffic.
18. 18 . The non-transitory computer-readable storage medium of claim 15 , wherein the first region of the memory sub-system and the second region of the memory sub-system correspond to regions associated with storing data items that are subject to a media management operation.
19. 19 . The non-transitory computer-readable storage medium of claim 15 , wherein the first memory pages correspond to a first memory page level of a first set of memory cells residing at the first region and the second memory pages to one or more second memory page levels of the first set of memory cells.
20. 20 . The non-transitory computer-readable storage medium of claim 15 , wherein the first region, the second region, and the third region of the memory sub-system each include at least one of a multi-level memory cell, a triple-level memory cell, or a quad-level memory cell.

Description

RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 17/715,799 filed Apr. 7, 2022, which claims the benefit of U.S. Provisional Patent Application No. 63/292,926, filed Dec. 22, 2021. The above-referenced applications are incorporated herein by reference. TECHNICAL FIELD Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to resequencing data programmed to multiple level memory cells at a memory sub-system. BACKGROUND A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only. FIG. 1 illustrates an example computing system that includes a memory sub-system, in accordance with some embodiments of the present disclosure. FIG. 2 is a flow diagram of an example method for resequencing data programmed to multiple level memory cells at a memory sub-system, in accordance with some embodiments of the present disclosure. FIGS. 3A-3B depict an example of resequencing data programmed to multiple level memory cells at a memory sub-system, in accordance with some embodiments of the present disclosure. FIG. 4 is a flow diagram of an example method for resequencing data programmed to multiple level memory cells at a memory sub-system via a memory management protocol, in accordance with some embodiments of the present disclosure. FIGS. 5A-C depict an example of resequencing data programmed to multiple level memory cells at a memory sub-system via a memory management protocol, in accordance with some embodiments of the present disclosure. FIG. 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION Aspects of the present disclosure are directed to resequencing data programmed to multiple level memory cells at a memory sub-system. A memory sub-system can be a storage device, a memory module, or a combination of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more memory components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. A memory sub-system can utilize one or more memory devices, including any combination of the different types of non-volatile memory devices and/or volatile memory devices, to store the data provided by the host system. In some embodiments, non-volatile memory devices can be provided by negative-and (NAND) type flash memory devices. Other examples of non-volatile memory devices are described below in conjunction with FIG. 1. A non-volatile memory device is a package of one or more dice. Each die can include one or more planes. A plane is a portion of a memory device that includes multiple memory cells. Some memory devices can include two or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. Each block includes a set of pages. “Block” herein shall refer to a set of contiguous or non-contiguous memory pages. An example of a “block” is an “erasable block,” which is the minimal erasable unit of memory, while “page” is a minimal writable unit of memory. Each page corresponds to a set of memory cells. A memory cell is an electronic circuit that stores information. In some instances, memory cells can be single level cells (SLCs) that are configured to store a single bit of data (e.g., a single data item, etc.). In other instances, memory cells can be configured to store multiple bits of data. For example, memory cells can be multi-level cells (MLCs), triple-level cells (TLCs), or quad-level cells (QLCs) (collectively referred to herein as XLCs or multiple level cells). Each memory cell type can have a different data density, which corresponds to an amount of data (e.g., bits of data, etc.) that can be stored per memory cell). Data operations can be performed by the memory sub-system. The data operations can be host-initiated operations. For example, the host system can initiate a data operation (e.g., write, read, erase, etc.) on a memory sub-system. The host system can send access requests (e.g., a programming command, a read command, etc.) to the memory sub-system, such as to store data on a memory devi