US-20260126930-A1 - CROSS-COMPARISON OF DATA COPY PAIRS DURING MEMORY DEVICE INITIALIZATION

US20260126930A1US 20260126930 A1US20260126930 A1US 20260126930A1US-20260126930-A1

Abstract

A memory device includes a local memory configured to store operational data comprising a plurality of copy pairs. A first multiplexer receives a plurality of copies from the plurality of copy pairs. A second multiplexer receives a plurality of inverted copies from the plurality of copy pairs, the plurality of inverted copies being inverted versions of the plurality of copies. Control logic coupled to selector inputs of the first and second multiplexers provides a time-varying selector signal to cycle through selecting from the plurality of copy pairs and inverted copies. The control logic changes the time-varying selector signal at clock cycle transitions of an internal clock to cause the multiplexers to sequentially output different copy pairs and inverted copies at the clock cycle transitions. Comparison logic coupled with the first and second multiplexers performs comparisons between each selected copy pair and each selected inverted copy.

Inventors

Angelo COVELLO
Claudia CIASCHI
Michele Incarnati
Tommaso Vali

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260507
Application Date: 20260107

Claims (20)

1 . A memory device comprising: a local memory configured to store operational data comprising a plurality of copy pairs; a first multiplexer configured to receive a plurality of copies from the plurality of copy pairs; a second multiplexer configured to receive a plurality of inverted copies from the plurality of copy pairs, the plurality of inverted copies being inverted versions of the plurality of copies; control logic coupled to selector inputs of the first multiplexer and the second multiplexer, the control logic configured to: provide a time-varying selector signal to cycle through selecting from the plurality of copy pairs received by the first multiplexer and the plurality of inverted copies received by the second multiplexer; and change the time-varying selector signal at clock cycle transitions of an internal clock to cause the first multiplexer and the second multiplexer to sequentially output different copy pairs and inverted copies, respectively, at the clock cycle transitions; and comparison logic coupled with the first multiplexer and the second multiplexer, the comparison logic configured to perform comparisons between each selected copy pair of the plurality of copy pairs and each selected inverted copy of the plurality of inverted copies.
2 . The memory device of claim 1 , wherein the comparison logic is further configured to: buffer each selected copy pair of the plurality of copy pairs and each selected inverted copy of the plurality of inverted copies; compare at least one buffered copy of the plurality of copy pairs with a different-numbered inverted copy of the plurality of inverted copies; and record one of a pass indicator or a fail indicator with each comparison.
3 . The memory device of claim 2 , wherein the comparison logic is further configured to: output, based on results of the comparison, a known valid copy of the operational data; and output the pass indicator based on availability of the known valid copy.
4 . The memory device of claim 2 , further comprising an accumulator coupled to an output of the comparison logic, the accumulator to: store any first valid data associated with a first plurality of compared pairs of the plurality of copy pairs with a corresponding one of the pass indicator or the fail indicator received from the comparison logic; store any second valid data associated with a second plurality of compared pairs of the plurality of copy pairs with a corresponding one of the pass indicator or the fail indicator received from the comparison logic; and output, as global data, a combination of the first valid data and the second valid data and one or more of a global pass indicator and a global fail indicator.
5 . A memory device comprising: a local memory configured to store operational data comprising at least a first copy pair and a second copy pair, the first copy pair comprising a first copy and an inverted first copy and the second copy pair comprising a second copy and an inverted second copy; comparison logic operatively coupled with the local memory, the comparison logic comprising: a first exclusive OR (XOR) gate configured to compare the first copy with the inverted first copy; a second XOR gate configured to compare the second copy with the inverted second copy; a third XOR gate configured to cross-compare one copy of the first copy pair with one copy of the second copy pair; an AND gate configured to receive, as inputs, outputs from the first XOR gate, the second XOR gate, and the third XOR gate; and a plurality of switches configured to selectively enable cross-comparison functionality of the first XOR gate, the second XOR gate, and the AND gate.
6 . The memory device of claim 5 , further comprising a set of multiplexers triggered by the comparison logic, wherein the set of multiplexers comprises: a first multiplexer configured to receive, as inputs, valid data corresponding to a copy of the operational data and an error code; and a second multiplexer configured to receive, as inputs, an output of the first multiplexer and valid data corresponding to another copy of the operational data.
7 . The memory device of claim 6 , wherein the set of multiplexers further comprises additional switches configured to selectively connect the error code to the first multiplexer when the cross-comparison functionality is enabled.
8 . The memory device of claim 6 , wherein the set of multiplexers further comprises a third multiplexer and a fourth multiplexer, wherein the third multiplexer and the fourth multiplexer are used when the cross-comparison functionality is disabled.
9 . The memory device of claim 5 , wherein the plurality of switches comprises: a first switch coupled to an output of the first XOR gate; a second switch coupled to an output of the second XOR gate; and a third switch coupled to an output of the AND gate, the third switch configured to selectively include a cross-comparing result between the first copy pair and the second copy pair.
10 . The memory device of claim 9 , wherein the plurality of switches are implemented as semiconductor switches or analog switches and each comprises a transmission gate.
11 . The memory device of claim 9 , wherein the plurality of switches are configured via metal options comprising one of: a physical mask or different metal traces.
12 . The memory device of claim 9 , wherein when the third switch is in an ON state and the cross-comparison is enabled, the comparison logic is configured to: compare the first copy with the inverted first copy using the first XOR gate; compare the second copy with the inverted second copy using the second XOR gate; cross-compare one of the first copy and the inverted second copy, or the inverted first copy and the second copy, using the third XOR gate; and detect an error based on outputs of the first XOR gate, the second XOR gate, and the third XOR gate using the AND gate.
13 . The memory device of claim 9 , wherein when the third switch is in an OFF state and the cross-comparison is disabled, the first switch and the second switch are in an ON state, and the comparison logic is configured to: compare the first copy with the inverted first copy using the first XOR gate; and compare the second copy with the inverted second copy using the second XOR gate, without performing the cross-comparison between the first copy pair and the second copy pair.
14 . The memory device of claim 9 , wherein the third XOR gate is configured to compare one of: the first copy and the inverted second copy; or the inverted first copy and the second copy.
15 . The memory device of claim 9 , wherein the comparison logic further comprises a second set of logic gates configured to compare a third copy pair and a fourth copy pair of the operational data, the second set of logic gates comprising: a fourth XOR gate configured to compare a third copy with an inverted third copy; a fifth XOR gate configured to compare a fourth copy with an inverted fourth copy; a sixth XOR gate configured to cross-compare one copy of the third copy pair with one copy of the fourth copy pair; and a second AND gate configured to receive, as inputs, outputs from the fourth XOR gate, the fifth XOR gate, and the sixth XOR gate.
16 . The memory device of claim 9 , further comprising a local media controller, wherein the comparison logic is configured to trigger loading the operational data into the local media controller in response to detecting the first copy pair matches the second copy pair.
17 . A memory device comprising: a local memory configured to store operational data comprising a plurality of copy pairs, each copy pair comprising a copy and an inverted copy; comparison logic operatively coupled with the local memory and configured to: compare copies and inverted copies of the plurality of copy pairs; cross-compare at least one copy of a first copy pair with at least one copy of a second copy pair; and output a pass indicator or a fail indicator for each comparison; and an accumulator coupled to an output of the comparison logic and configured to: store first valid data associated with a first plurality of cross-compared pairs of copies with a corresponding pass indicator or fail indicator received from the comparison logic; store second valid data associated with a second plurality of cross-compared pairs of copies with a corresponding pass indicator or fail indicator received from the comparison logic; aggregate the first valid data and the second valid data; and output, as global data, a combination of the first valid data and the second valid data with a global pass indicator or a global fail indicator based on the aggregated first and second valid data.
18 . The memory device of claim 17 , wherein the accumulator is configured to output the global fail indicator only when no previous valid check has passed the comparison for the plurality of cross-compared pairs of copies.
19 . The memory device of claim 17 , wherein the accumulator is further configured to: buffer each copy of the plurality of copies that is compared by the comparison logic; and output, as the global data and after comparison of all copies of the plurality of copy pairs, at least one copy of the plurality of copies with the global pass indicator or the global fail indicator.
20 . The memory device of claim 17 , wherein the accumulator is further configured to at least one of: store information identifying each respective copy and inverted copy that is compared along with the pass indicator or the fail indicator received from the comparison logic for each respective comparison; or output, based on previously resolved valid data from the comparison logic, a copy of the operational data that was previously resolved as valid data when a subsequent comparison results in an error.

Description

CLAIM OF PRIORITY The present application is a continuation of U.S. application Ser. No. 18/509,587, filed Nov. 15, 2023, which claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application No. 63/437,797 filed Jan. 9, 2023, which are incorporated by reference herein. TECHNICAL FIELD Embodiments of the disclosure relate generally to memory sub-systems, and more cross-comparison of data copy pairs during memory device initialization. BACKGROUND A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1A illustrates an example computing system that includes a memory sub-system according to embodiments. FIG. 1B is a block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system, in accordance with some embodiments. FIG. 2 is a flow chart of a method for cross-comparing data copy pairs according to various embodiments. FIG. 3A is a block diagram of comparison logic for comparing copy pairs of operational data including cross-comparing between the copy pairs according to an embodiment. FIG. 3B is a block diagram of comparison logic for comparing copy pairs of operational data including an optional metal option for selective removal of the cross-comparing according to an embodiment. FIG. 3C is a block diagram of comparison logic for comparing copy pairs of operational data including cross-comparing between the copy pairs according to at least another embodiment. FIG. 4 is a flow chart of a method for comparing copy pairs of operational data including cross-comparing between the copy pairs according to various embodiments. FIG. 5 is a block diagram of comparison logic for comparing copy pairs of operational data including cross-comparing between the copy pairs according to at least one embodiment. FIG. 6A is a block diagram of a data comparison architecture for sequentially comparing copy pairs that supports cross-comparing between the copy pairs according to an embodiment. FIG. 6B is a graph with a set of plots illustrating the functionality of the data comparison architecture of FIG. 6A according to at least one embodiment. FIG. 7 is a block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION Aspects of the present disclosure are directed to cross-comparison of data copy pairs during memory device initialization. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1A. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. The memory devices can be non-volatile memory devices that can store data from the host system. One example of a non-volatile memory device is a NOT-AND (NAND) memory device. Other examples of non-volatile memory devices are described below in conjunction with FIG. 1. Each of the memory devices can include one or more arrays of memory cells that are organized in physical blocks of memory cells. A memory cell (“cell”) is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1,” or combinations of such values. A NAND memory device, also sometimes referred to as NAND flash memory, employs circuitry that allows proper initialization of the memory device at power-on, sometimes referred to as power-on reset (POR). The circuitry may be configured to initialize the memory device with a probability of error in operational data lower than 20 defects per million (dpm), although stricter probabilities of error are expected in the future. For example, operational data is usually read out of a read only memory (ROM) of the memory device, and after some error checking, is loaded into a local media controller that controls the operation of the memory device. Bad initialization of the memory device leads to a wrong operational data being loaded and the memory device not working as expected, e.g., device or system errors. Systems require continuous improvement in performances, therefore requiring safe areas where data can be stored wit