US-20260126931-A1 - METHODS AND APPARATUSES FOR OPERATING A MEMORY SYSTEM

Abstract

Methods, devices, and systems for managing memory devices are provided. In one aspect, a memory system can include a memory device including memory pages, a memory controller coupled to the memory device. The memory controller is configured to send, to the memory device, a first command indicating to identify dummy data, and in response to receiving, from the memory device, a response indicating that a first memory page is a zero page, determine data comprised in the first memory page as dummy data.

Inventors

• Xingwei Tang
• Lu Guo
• Kun Ren
• Wen Luo

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260507

Application Date

20250114

Claims (20)

1. 1 . A memory system, comprising: a memory device comprising memory pages; and a memory controller coupled to the memory device, wherein the memory controller is configured to: send, to the memory device, a first command indicating to identify dummy data; and in response to receiving, from the memory device, a response indicating that a first memory page is a zero page, determine data comprised in the first memory page as dummy data.
2. 2 . The memory system of claim 1 , wherein the memory controller is further configured to: send a second command indicating to write dummy data in a second memory page, wherein the memory device is configured to: in response to receiving the second command, program the second memory page into a zero page, wherein threshold voltages of memory cells of the zero page are higher than a preset level, wherein the preset level is higher than a starting read level for reading the second memory page.
3. 3 . The memory system of claim 2 , wherein the second command indicates to program the second memory page based on a single-level cell (SLC) mode.
4. 4 . The memory system of claim 3 , wherein programming the second memory page based on the SLC mode comprises: programming, using a single program pulse, memory cells of the second memory page above the preset level.
5. 5 . The memory system of claim 2 , wherein a low density parity check (LDPC) encoder of the memory controller is disabled when programming the second memory page.
6. 6 . The memory system of claim 1 , wherein the memory device is configured to: send the response indicating that the first memory page is a zero page, without sending the data comprised in the first memory page to the memory controller.
7. 7 . The memory system of claim 1 , wherein the memory device is configured to: perform, based on a starting read voltage, a read operation on the first memory page; determine a quantity of failed memory cells in the first memory page, wherein threshold voltages of the failed memory cells are lower than the starting read voltage; and in response to determining that the quantity of failed memory cells is less than a threshold, send the response indicating that the first memory page is a zero page.
8. 8 . The memory system of claim 1 , wherein the memory controller is configured to send the first command during a garbage collection operation of the memory system.
9. 9 . The memory system of claim 2 , wherein the memory controller is configured to send the second command during a power-loss protection operation, wherein the second memory page is comprised in an open memory block.
10. 10 . The memory system of claim 2 , wherein the memory controller is configured to send the second command after a program operation for programming user data into one or more memory pages, wherein the second memory page immediately follows a last memory page of the one or more memory pages.
11. 11 . A memory controller, comprising: at least one processor and an interface, wherein the at least one processor is configured to: send, through the interface to a memory device, a first command that indicates to identify dummy data; and in response to receiving, through the interface from the memory device, a response indicating that a first memory page is a zero page, determine data comprised in the first memory page as dummy data.
12. 12 . The memory controller of claim 11 , wherein the memory controller is configured to: send a second command indicating to write dummy data in a second memory page, wherein the second command indicates to program the second memory page based on a single-level cell (SLC) mode.
13. 13 . The memory controller of claim 12 , wherein a low density parity check (LDPC) encoder of the memory controller is disabled when programming the second memory page.
14. 14 . The memory controller of claim 12 , wherein the memory controller is configured to send the second command during a power-loss protection operation, wherein the second memory page is comprised in an open memory block.
15. 15 . The memory controller of claim 12 , wherein the memory controller is configured to send the second command after a program operation for programming user data into one or more memory pages, wherein the second memory page immediately follows a last memory page of the one or more memory pages.
16. 16 . The memory controller of claim 11 , wherein the memory controller is configured to send the first command during a garbage collection operation.
17. 17 . A method of operating a memory system, comprising: sending, from a memory controller of the memory system to a memory device of the memory system, a first command that indicates to identify dummy data; and in response to receiving, by the memory controller from the memory device, a response indicating that a first memory page of the memory device is a zero page, determining data comprised in the first memory page as dummy data.
18. 18 . The method of claim 17 , further comprising: performing, based on a starting read voltage, a read operation on the first memory page; determining a quantity of failed memory cells in the first memory page, wherein threshold voltages of the failed memory cells are lower than the starting read voltage; and in response to determining that the quantity of failed memory cells is less than a threshold, sending, from the memory device to the memory controller, the response indicating that the first memory page is a zero page.
19. 19 . The method of claim 17 , comprising: sending, from the memory controller to the memory device, a second command indicating to write dummy data in a second memory page of the memory device; and programming, by the memory device, the second memory page into a zero page, wherein threshold voltages of memory cells of the zero page are higher than a preset level, wherein the preset level is higher than a starting read level for reading the second memory page.
20. 20 . The method of claim 17 , comprising: sending, from the memory device to the memory controller, the response indicating that the first memory page is a zero page, without sending the data comprised in the first memory page.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Application No. PCT/CN2024/129600, filed on Nov. 4, 2024, the disclosure of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD The present disclosure generally relates to memory devices and memory systems, and in particular, to programming and identifying dummy data in memory systems. BACKGROUND Flash memory is a low-cost, high-density, nonvolatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed by flash memory, for example, program (write) and erase operations, to change the threshold voltage of each memory cell to a respective level. For NAND flash memory, an erase operation can be performed at the memory block level, a program operation can be performed at the page level, and a read operation can be performed at the page level. SUMMARY The present disclosure involves methods, apparatuses, and systems for programming and identifying dummy data in a memory system. One aspect of the present disclosure features a memory system including a memory device including memory pages, and a memory controller coupled to the memory device. The memory controller is configured to send to the memory device a first command indicating to identify dummy data, and in response to receiving from the memory device a response indicating that a first memory page is a zero page, determine data included in the first memory page as dummy data. In some implementations, the memory controller is further configured to send a second command indicating to write dummy data in a second memory page. The memory device is configured to, in response to receiving the second command, program the second memory page into a zero page. Threshold voltages of memory cells of the zero page are higher than a preset level. The preset level is higher than a starting read level for reading the second memory page. In some implementations, the second command indicates to program the second memory page based on a single-level cell (SLC) mode. In some implementations, programming the second memory page based on the SLC mode includes programming, using a single program pulse, memory cells of the second memory page above the preset level. In some implementations, a low density parity check (LDPC) encoder of the memory controller is disabled when programming the second memory page. In some implementations, the memory device is configured to send the response indicating that the first memory page is a zero page, without sending the data included in the first memory page to the memory controller. In some implementations, the memory device is configured to perform, based on a starting read voltage, a read operation on the first memory page; determine a quantity of failed memory cells in the first memory page, where threshold voltages of the failed memory cells are lower than the starting read voltage; and in response to determining that the quantity of failed memory cells is less than a threshold, send the response indicating that the first memory page is a zero page. In some implementations, the memory controller is configured to send the first command during a garbage collection operation of the memory system. In some implementations, the memory controller is configured to send the second command during a power-loss protection operation. The second memory page is included in an open memory block. In some implementations, the memory controller is configured to send the second command after a program operation for programming user data into one or more memory pages. The second memory page immediately follows a last memory page of the one or more memory pages. Another aspect of the present disclosure features a memory controller. The memory controller includes at least one processor and an interface. The at least one processor is configured to send, through the interface to a memory device, a first command that indicates to identify dummy data; and in response to receiving, through the interface from the memory device, a response indicating that a first memory page is a zero page, determine data included in the first memory page as dummy data. In some implementations, the memory controller is configured to send a second command indicating to write dummy data in a second memory page. The second command indicates to program the second memory page based on a single-level cell (SLC) mode. In some implementations, a low density parity check (LDPC) encoder of the memory controller is disabled when programming the second memory page. In some implementations, the memory controller is configured to send the second command during a power-loss protection operation. The second memory page is included in an open memory block. In some implementations, the memory controller is configured to send the second command after a program operation for p