US-20260127001-A1 - POWER EFFICIENT MULTI-BIT STORAGE SYSTEM

US20260127001A1US 20260127001 A1US20260127001 A1US 20260127001A1US-20260127001-A1

Abstract

Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.

Inventors

Kai-Chi HUANG
Chi-Lin Liu
Wei-Hsiang Ma
Shang-Chih Hsieh

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20251229

Claims (20)

1 . A clock gating circuit comprising: a plurality of logic gates, to: receive an enable signal derived from a comparison between an input and an output of at least one storage circuit; and output a trigger signal in a first state for a duration based on the enable signal.
2 . The clock gating circuit of claim 1 , comprising a plurality of transistors, wherein at least one of the plurality of logic gates comprises a subset of the plurality of transistors, and wherein the plurality of transistors comprise one or more n-type transistors and one or more p-type transistors.
3 . The clock gating circuit of claim 1 , wherein the plurality of logic gates comprise at least one NAND gate and at least one inverter.
4 . The clock gating circuit of claim 1 , wherein the input and the output of the at least one storage circuit is from one clock cycle.
5 . The clock gating circuit of claim 1 , wherein at least one of the plurality of logic gates is to: receive a clock signal, wherein the duration corresponds to a duration of the clock signal.
6 . The clock gating circuit of claim 5 , wherein the duration of the clock signal comprises is from a rising edge of the clock signal to a falling edge of the clock signal, and wherein the at least one of the plurality of logic gates is to: receive the enable signal responsive to the rising edge of the clock signal; and output the trigger signal in the first state from the rising edge to the falling edge of the clock signal.
7 . The clock gating circuit of claim 1 , wherein the comparison between the input and the output correspond to a predicted change in a state at an output port of the at least one storage circuit, and wherein to receive the enable signal, at least one of the plurality of logic gates is to: receive the enable signal from a prediction circuit, wherein the prediction circuit is to generate the enable signal based on the predicted change responsive to receiving the input and the output from the at least one storage circuit.
8 . The clock gating circuit of claim 7 , wherein the prediction circuit comprises: at least one XOR gate to receive the input and the output of the at least one storage circuit as a first input and a second input, and generate a signal based on the first input and the second input; and at least one OR gate to output the enable signal based on the signal from the at least one XOR gate.
9 . The clock gating circuit of claim 1 , wherein at least one of the plurality of logic gates is to: output the trigger signal in a second state after the duration.
10 . The clock gating circuit of claim 1 , wherein at least one of the plurality of logic gates is to: output the trigger signal to the at least one storage circuit, wherein the trigger signal corresponds to a clock signal of the at least one storage circuit.
11 . An integrated circuit, comprising: a clock gating circuit, to: receive an enable signal derived from a comparison between an input and an output of at least one storage circuit; and adjust a trigger signal between a first state and a second state based on the enable signal.
12 . The integrated circuit of claim 11 , comprising: a first storage circuit comprising the at least one storage circuit; and a second storage circuit, wherein outputs from the first storage circuit and the second storage circuit are updated responsive to the trigger signal.
13 . The integrated circuit of claim 12 , comprising a prediction circuit, wherein: the first storage circuit and the second storage circuit are disposed between the prediction circuit and the clock gating circuit, or the prediction circuit and the clock gating circuit are disposed between the first storage circuit and the second storage circuit.
14 . The integrated circuit of claim 11 , comprising: a prediction circuit to: receive the input and the output of the at least one storage circuit; perform the comparison between the input and the output; and generate the enable signal based on the comparison, wherein the enable signal is indicative of whether a state of the output of the at least one storage circuit is predicted to be changed.
15 . The integrated circuit of claim 14 , wherein to adjust the trigger signal, the clock gating circuit is to: adjust the trigger signal to the first state based on the enable signal indicating that the output is predicted to change the state; and adjust the trigger signal to the second state subsequent to a duration.
16 . The integrated circuit of claim 14 , wherein the at least one storage circuit comprises a first storage circuit and a second storage circuit, and wherein the prediction circuit comprises: a plurality of logic gates comprising a first logic gate, a second logic gate, and a third logic gate, wherein: the first logic gate to receive a first input and a first output from the first storage circuit and generate a first prediction signal based on the first input and the first output, the second logic gate to receive a second input and a second output from the second storage circuit and generate a second prediction signal based on the second input and the second output, and the third logic gate to receive the first prediction signal and the second prediction signal and generate the enable signal based on the first prediction signal and the second prediction signal.
17 . The integrated circuit of claim 11 , wherein the clock gating circuit is to: adjust the trigger signal to one of the first state or the second state responsive to a rising edge of a clock signal; and adjust the trigger signal to another one of the first state or the second state responsive to a falling edge of the clock signal.
18 . A method, comprising: forming a clock gating circuit, comprising a logic gates, to: receive an enable signal derived from a comparison between an input and an output of at least one storage circuit; and output a trigger signal in a first state for a duration based on the enable signal.
19 . The method of claim 18 , comprising: forming the at least one storage circuit; and forming a prediction circuit, wherein the prediction circuit is to: receive the input and the output of the at least one storage circuit; generate the enable signal based on the comparison between the input and the output of the at least one storage circuit; and output the enable signal to the clock gating circuit.
20 . The method of claim 18 , wherein forming the clock gating circuit comprises: forming a plurality of logic gates comprising at least one inverter and at least one NAND gate, wherein the at least one NAND gate is to receive the enable signal and a clock signal to generate a signal, and wherein the at least one inverter is to receive the signal from the at least one NAND gate to generate the trigger signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. patent application Ser. No. 18/886,319, filed Sep. 16, 2024, which is a continuation of U.S. patent application Ser. No. 17/859,377, filed Jul. 7, 2022, which claims the benefit of and priority to U.S. patent application Ser. No. 16/900,514, filed Jun. 12, 2020, which are incorporated herein by reference in their entireties for all purposes. BACKGROUND Developments in an integrated circuit design allow an integrated circuit to perform complex functionalities. In one aspect, an integrated circuit includes digital logic circuits that can perform logic computations based on electrical signals (e.g., voltage or current) representing corresponding bits of data. For example, a signal having 1V can represent a state or a logic value ‘1’, where a signal having 0V can represent a state or a logic value ‘0’. In various applications, synchronous logic circuits can perform various logic computations synchronously based on a clock signal. To enable synchronous logic computations, flip flops or latches can store or hold data for a time period, according to the clock signal. Data held or stored by the flip flops or the latches enable one or more logic computations to be performed in a reliable manner. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic diagram of a multi-bit storage system, in accordance with one implementation. FIG. 2 is a schematic diagram of an example prediction circuit of the multi-bit storage system shown in FIG. 1, in accordance with some embodiments. FIG. 3 is a schematic diagram of an XOR gate of the prediction circuit shown in FIG. 2, in accordance with some embodiments. FIG. 4 is a schematic diagram of an OR gate of the prediction circuit shown in FIG. 2, in accordance with some embodiments. FIG. 5 is a schematic diagram of a clock gating circuit of the multi-bit storage system shown in FIG. 1, in accordance with some embodiments. FIG. 6 is an example timing diagram of an operation of a multi-bit storage system, in accordance with some embodiments. FIG. 7 is a flowchart of a method of operation of a multi-bit storage system, in accordance with some embodiments. FIG. 8 is an example layout diagram of a multi-bit storage system, in accordance with some embodiments. FIG. 9 is an example block diagram of a computing system, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Disclosed herein are embodiments related to an integrated circuit including a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicatin