US-20260127073-A1 - MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM

US20260127073A1US 20260127073 A1US20260127073 A1US 20260127073A1US-20260127073-A1

Abstract

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller is configured to generate first parity based on first data in a first memory system and second data in a second memory system, writes the first parity to the nonvolatile memory, receive third data that is updated data of the first data from a host, receive the first data from the first memory system, read the first parity from the nonvolatile memory, generate second parity based on the first parity, the first data, and the third data, generate first rebuilt data based on the second parity, the first parity, and the first data, and compare the first rebuilt data with the third data.

Inventors

Hiroyasu NAKATSUKA
Devesh Kumar Rai

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260507
Application Date: 20241212

Claims (20)

1 . A memory system comprising: an interface circuit communicable with a host and a plurality of external memory systems, the plurality of external memory systems including at least a first memory system and a second memory system; a nonvolatile memory; and a controller configured to: generate a first parity, based on first data stored in the first memory system and second data stored in the second memory system; write the first parity to the nonvolatile memory; receive third data from the host via the interface circuit, the third data being updated data of the first data; receive the first data from the first memory system via the interface circuit; read the first parity from the nonvolatile memory; generate a second parity, based on the first parity, the first data, and the third data; generate first rebuilt data, based on the second parity, the first parity, and the first data; and compare the first rebuilt data with the third data received from the host.
2 . The memory system of claim 1 , wherein the controller is further configured to write the second parity to the nonvolatile memory if the first rebuilt data matches the third data received from the host.
3 . The memory system of claim 2 , wherein the controller is further configured to: transfer a first response indicative of success in generation of the second parity to the host via the interface circuit if the first rebuilt data matches the third data received from the host; and transfer a second response indicative of failure in generation of the second parity to the host via the interface circuit if the first rebuilt data does not match the third data received from the host.
4 . The memory system of claim 1 , wherein the controller is further configured to generate the first parity by calculating exclusive OR of the first data and the second data.
5 . The memory system of claim 4 , wherein the controller is further configured to generate the second parity by calculating exclusive OR of the first parity, the first data, and the third data.
6 . The memory system of claim 1 , wherein the controller is further configured to: receive fourth data from the host via the interface circuit, the fourth data being updated data of the second data; generate a third parity, based on the third data and the fourth data; generate second rebuilt data, based on the third parity and the fourth data; and compare the second rebuilt data with the third data received from the host.
7 . The memory system of claim 6 , wherein the controller is further configured to write the third parity to the nonvolatile memory if the second rebuilt data matches the third data received from the host.
8 . The memory system of claim 7 , wherein the controller is further configured to: transfer a third response indicative of success in generation of the third parity to the host via the interface circuit if the second rebuilt data matches the third data received from the host; and transfer a fourth response indicative of failure in generation of the third parity to the host via the interface circuit if the second rebuilt data does not match the third data received from the host.
9 . The memory system of claim 1 , wherein the controller is further configured to: receive the first data from the host via the interface circuit; receive the second data from the host via the interface circuit; generate the first parity, based on the first data and the second data; generate third rebuilt data, based on the first parity and the second data; and compare the third rebuilt data with the first data received from the host.
10 . The memory system of claim 1 , wherein the controller is further configured to transfer the third data received from the host, to the first memory system via the interface circuit.
11 . An information processing system, comprising: a host; and a plurality of memory systems each including a nonvolatile memory and a controller electrically connected to the nonvolatile memory, the plurality of memory systems including at least a first memory system, a second memory system, and a third memory system; a first controller that is the controller of the first memory system is configured to store first data in a first nonvolatile memory that is the nonvolatile memory of the first memory system; a second controller that is the controller of the second memory system is configured to store second data in a second nonvolatile memory that is the nonvolatile memory of the second memory system; a third controller that is the controller of the third memory system is configured to: generate a first parity, based on the first data and the second data; store the first parity in a third nonvolatile memory that is the nonvolatile memory of the third memory system; receive third data from the host, the third data being updated data of the first data; receive the first data from the first controller; read the first parity from the third nonvolatile memory; generate a second parity, based on the first parity, the first data, and the third data; generate first rebuilt data, based on the second parity, the first parity, and the first data; and compare the first rebuilt data with the third data received from the host.
12 . The information processing system of claim 11 , wherein the third controller is further configured to transfer a first response indicative of success in generation of the second parity to the host if the first rebuilt data matches the third data received from the host; the host is further configured to transfer a first write command requesting to write the second parity to the third memory system, in response to receiving the first response; and the third controller is further configured to write the second parity to the third nonvolatile memory in response to receiving the first write command.
13 . The information processing system of claim 11 , wherein the third controller is further configured to transfer a second response indicative of failure in generation of the second parity to the host if the first rebuilt data does not match the third data received from the host.
14 . The information processing system of claim 11 , wherein the third controller is further configured to: generate the first parity by calculating exclusive OR of the first data and the second data; and generate the second parity by calculating exclusive OR of the first parity, the first data, and the third data.
15 . The information processing system of claim 11 , wherein the third controller is further configured to: receive fourth data from the host, the fourth data being updated data of the second data; generate a third parity, based on the third data and the fourth data; generate second rebuilt data, based on the third parity and the fourth data; and compare the second rebuilt data with the third data received from the host.
16 . The information processing system of claim 15 , wherein the third controller is further configured to transfer a third response indicative of success in generation of the third parity to the host if the second rebuilt data matches the third data received from the host; the host is further configured to transfer a second write command requesting to write the third parity to the third memory system, in response to receiving the third response; and the third controller is further configured to write the third parity to the third nonvolatile memory in response to receiving the second write command.
17 . The information processing system of claim 11 , wherein the third controller is further configured to: receive the first data from the host; receive the second data from the host; generate the first parity, based on the first data and the second data; generate third rebuilt data, based on the first parity and the second data; and compare the third rebuilt data with the first data received from the host.
18 . The information processing system of claim 11 , wherein the third controller is further configured to transfer the third data received from the host, to the first controller.
19 . The information processing system of claim 11 , wherein the plurality of memory systems further include a fourth memory system, and a fourth controller that is the controller of the fourth memory system is configured to: generate a fourth parity, based on the first data and the second data; store the fourth parity in a fourth nonvolatile memory that is the nonvolatile memory of the fourth memory system; receive the third data from the host; receive the first data from the first controller; generate a fifth parity, based on the fourth parity, the first data, and the third data; generate fourth rebuilt data, based on the fifth parity, the fourth parity, and the first data; and compare the fourth rebuilt data with the third data received from the host.
20 . The information processing system of claim 19 , wherein the fourth controller is configured to: generate the fourth parity by calculating exclusive OR of the first data and the second data using a coefficient different from a coefficient used for generation of the first parity; and generate the fifth parity by calculating exclusive OR of the fourth parity, the first data, and the third data using a coefficient different from a coefficient used for generation of the second parity.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63/687,839, filed Aug. 28, 2024, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a memory system and an information processing system. BACKGROUND In recent years, a memory system and an information processing system have been widely prevalent. The memory system includes a nonvolatile memory. The information processing system includes a host. A solid state drive (SSD) including a NAND flash memory is known as such a memory system. The SSD is used as a main storage of various computing devices. To improve fault tolerance of the information processing system, a redundant array of inexpensive (or independent) disks (RAID) is often used. The RAID relates to a technology of storing data in a plurality of memory systems to improve redundancy and access performance of stored data. For example, in RAID-5, data and parities for data are dispersed and stored in a plurality of memory systems. An example of the parity is an error correction code (ECC). Therefore, for example, even if a memory system which stores some data fails, the data stored in the failed memory system can be rebuilt using other data and parities stored in other memory systems. Another example of the RAID is RAID-6 which stores two parities for data. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating an example of a configuration of an information processing system according to an embodiment. FIG. 2 is a block diagram illustrating an example of the configuration of a memory system according to the embodiment. FIG. 3 is a diagram illustrating an example of RAID-6 configured by the memory system according to the embodiment. FIG. 4 is a flowchart illustrating an example of a processing sequence of partial update according to the embodiment. FIG. 5 is a flowchart illustrating an example of a processing sequence of full stripe write according to the embodiment. DETAILED DESCRIPTION Embodiments will be described hereinafter with reference to the accompanying drawings. In the following descriptions, a device and a method are illustrated to embody the technical concept of the embodiments. The technical concept is not limited to the configuration, shape, arrangement, material or the like of the structural elements described below. Modifications that could easily be conceived by a person with ordinary skill in the art are naturally included in the scope of the disclosure. To make the descriptions clearer, the drawings may schematically show the size, thickness, planer dimension, shape, and the like of each element differently from those in the actual aspect. The drawings may include elements that differ in dimension and/or ratio. Elements corresponding to each other in the drawings are denoted by the same reference numeral and their redundant descriptions may be omitted. Some elements may be denoted by different names, and these names are merely an example. It should not be denied that one element is denoted by different names. Note that “connection” means that one element is connected to another element via still another element as well as that one element is directly connected to that another element. If the number of elements is not specified as plural, the elements may be singular or plural. In general, according to one embodiment, a memory system includes an interface circuit communicable with a host and a plurality of external memory systems, a nonvolatile memory, and a controller. The plurality of external memory systems include at least a first memory system and a second memory system. The controller is configured to generate a first parity based on first data stored in the first memory system and second data stored in the second memory system, write the first parity to the nonvolatile memory, receive third data that is updated data of the first data from the host via the interface circuit, receive the first data from the first memory system via the interface circuit, read the first parity from the nonvolatile memory, generate second parity based on the first parity, the first data, and the third data, generate first rebuilt data based on the second parity, the first parity, and the first data, and compare the first rebuilt data with the third data received from the host. (Example of Configuration of Information Processing System) FIG. 1 is a diagram illustrating an example of a configuration of an information processing system 1 according to an embodiment. The information processing system 1 includes a host device 2, a plurality of memory systems 3, and a switch 4. The host device 2 may be a storage server, a server, or a personal computer which stores a large amount of various types of data in the plurality of memory systems 3. In this specification, the host device 2 is referred to as a host 2. The plurality of memory systems 3 constitute RAID-5 or RA