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US-20260127074-A1 - MEMORY DEVICE STACK AVAILABILITY

US20260127074A1US 20260127074 A1US20260127074 A1US 20260127074A1US-20260127074-A1

Abstract

As information is written to a memory device stack, partial parity information is calculated by the non-parity devices in the stack from the information being written to that device and parity information received from the next lower device in the stack (if any). The partial parity information calculated by each non-parity device is transmitted to the next higher device in the stack so that it may perform a partial parity calculation using the partial parity information collectively calculated by the devices lower in the stack. Once complete parity has been collectively calculated by all of the non-parity devices in the stack, the complete parity information is stored by the parity memory device. The complete parity information may be used to recover or reconstruct data from a failing device in the stack by calculating and transmitting parity information from non-failing devices to the failing device and/or the parity device.

Inventors

  • Dongyun Lee
  • Wendy Elsasser
  • John Eric Linstadt

Assignees

  • RAMBUS INC.

Dates

Publication Date
20260507
Application Date
20231016

Claims (20)

  1. 1 . An integrated circuit stack, comprising: a first memory device comprising at least a first memory array and first through-silicon vias (TSVs); a second memory device comprising at least a second memory array, second TSVs, and parity calculation circuitry to calculate first parity information based on first information received from the first TSVs and second information to be stored in the second memory array, the second memory device to transmit the first parity information via the second TSVs; and a third memory device comprising at least a third memory array, the third memory device to receive the first parity information from the second TSVs and to store the first parity information in the third memory array.
  2. 2 . The integrated circuit stack of claim 1 , wherein the first information is second parity information based on third information to be stored in a fourth memory array of a fourth memory device in the integrated circuit stack.
  3. 3 . The integrated circuit stack of claim 1 , wherein the second memory device is to calculate calculated first information based on the first parity information received from the third memory device and the first information received from the first memory device.
  4. 4 . The integrated circuit stack of claim 3 , wherein the second memory device is to transmit, to a device external to the integrated circuit stack, the calculated first information.
  5. 5 . The integrated circuit stack of claim 1 , wherein the third memory device is to calculate calculated second information based on the first parity information retrieved from the third memory array and the first information received via the second memory device.
  6. 6 . The integrated circuit stack of claim 5 , wherein the third memory device is to store the second information in the third memory array.
  7. 7 . The integrated circuit stack of claim 6 , wherein the third memory device is to transmit the second information retrieved from the third memory array to a device external to the integrated circuit stack.
  8. 8 . An assembly, comprising: an external command/address (CA) interface to receive commands and addresses from a device external to the assembly; a first memory integrated circuit coupled to the external CA interface and comprising a first memory array, a first data interface, a first above parity interface, a first below parity interface, and first parity calculation circuitry; a second memory integrated circuit coupled to the external CA interface and being stacked with the first memory integrated circuit, the second memory integrated circuit comprising a second memory array, a second data interface, a second above parity interface, a second below parity interface, and second parity calculation circuitry, the second below parity interface being electrically coupled to the first above parity interface, the second parity calculation circuitry to calculate first parity information based on first information received via the second below parity interface and second information received via the second data interface; and a third memory integrated circuit coupled to the external CA interface and comprising a third memory array and a third below parity interface to receive the first parity information, the third memory integrated circuit to store, in the third memory array, the first parity information.
  9. 9 . The assembly of claim 8 , wherein the first memory integrated circuit is to base the first information on third information received via the first data interface.
  10. 10 . The assembly of claim 9 , wherein the first memory integrated circuit is to transmit the first information to the second below parity interface.
  11. 11 . The assembly of claim 8 , wherein the third memory integrated circuit is to transmit, via the third below parity interface and to the second memory integrated circuit, second parity information retrieved from the third memory array.
  12. 12 . The assembly of claim 11 , wherein the first memory integrated circuit is to transmit, via the first above parity interface and to the second memory integrated circuit, third parity information, the third parity information based on first data information retrieved from the first memory array and fourth parity information received via the first below parity interface.
  13. 13 . The assembly of claim 12 , wherein the second memory integrated circuit is to transmit, via the second data interface and to the device external to the assembly, second data information, the second data information based on third parity information received via the second below parity interface and the second parity information transmitted by the third memory integrated circuit.
  14. 14 . The assembly of claim 8 , wherein the third memory integrated circuit is to recalculate the second information based on the first parity information retrieved from the third memory array and third parity information received from the second memory integrated circuit.
  15. 15 . The assembly of claim 14 , wherein the third memory integrated circuit is to store the second information in the third memory array.
  16. 16 . A method, comprising: receiving, by a first memory device in a memory integrated circuit device stack, a first write access command; and in response to the first write access command, writing first parity information to a first memory array of the first memory device, the first parity information based on parity information calculated by a plurality of other memory devices in the memory integrated circuit device stack, the first parity information being calculated by the plurality of other memory devices in the memory integrated circuit device stack in response to the first write access command.
  17. 17 . The method of claim 16 , further comprising: configuring the first memory device to write the first parity information to the first memory array.
  18. 18 . The method of claim 17 , further comprising: configuring the plurality of other memory devices to collectively calculate the first parity information.
  19. 19 . The method of claim 16 , further comprising: configuring the memory integrated circuit device stack to replace a failing one of the plurality of other memory devices using information stored by the first memory device.
  20. 20 . The method of claim 16 , further comprising: configuring the memory integrated circuit device stack to reproduce information stored by a failing one of the plurality of other memory devices; and storing the reproduced information in the first memory device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A-1H are notional diagrams illustrating a memory device stack. FIGS. 2A-2C are example timing diagrams illustrating memory device stack operations. FIG. 3 is a flowchart illustrating a method of operating a memory device stack. FIG. 4 is a flowchart illustrating a method of operating a memory device stack having a failed device. FIG. 5 is a flowchart illustrating a method of recovering information stored in a memory device stack having a failed device. FIG. 6 is a block diagram of a processing system. DETAILED DESCRIPTION OF THE EMBODIMENTS In an embodiment, a stack of memory devices includes a parity memory device to store parity information. As information is written to the memory device stack, partial parity information is calculated by the non-parity devices in the stack from the information being written to that device and parity information received from the next lower device in the stack (if any). The partial parity information calculated by each non-parity device is transmitted to the next higher device in the stack so that it may perform a partial parity calculation using the partial parity information collectively calculated by the devices lower in the stack. Once complete parity has been collectively calculated by all of the non-parity devices in the stack, the complete parity information is stored by the parity memory device. In an embodiment, in the event of a failure of a non-parity device, the memory device stack is configured to recreate the information being read from the failed device using the parity from the parity device and the information being read from the non-failing non-parity devices. In particular, the complete parity information is read from the parity device and transmitted to the next lower device in the stack. Each non-parity device then calculates partial recovery parity information using information read from its array and the information received from an adjacent device. The partial recovery parity calculated by each non-failing device is transmitted in the direction (up or down) leading to the failing device. The failing device receives partial recovery parity information adjacent device(s) and is able to recreate the information originally stored by it using this information. In an embodiment, in the event of a failure of a non-parity device, the memory device is configured to recreate the information stored by the failing non-parity device in the parity memory device. In particular, each non-failing non-parity device calculates partial parity information from the information read from that device and parity information received from the next lower device in the stack (if any). The partial parity information calculated by each non-parity device is transmitted to the next higher device in the stack so that it may perform a partial parity calculation using the partial parity information collectively calculated by the devices lower in the stack. Once a recovery parity has been collectively calculated by all of the non-failing non-parity devices in the stack, the recovery parity information is transmitted to the parity memory device. The parity memory device calculates the information originally stored by the failing device from the recovery parity information, and the complete parity information read from the array of the parity memory device. The recovered information originally stored by the failing device is then written back to the array of the parity memory device. This process may be repeated for every location of the memory device stack in order to allow the parity memory device to replace the functionality of the failed non-parity device. FIGS. 1A-1H are notional diagrams illustrating a memory device stack. In FIGS. 1A-1H, memory system 100 comprises stacked die component 110 and controller 120. Stacked die component 110 includes memory integrated circuit (IC) dies 130a-130e, command/address (CA) interface 145, and data (DQ) interface 143. Each of memory integrated circuit die 130a-130e each respectively include DQ interface 131a-131e, parity “A” (“above”) interface 132a-132e, parity “B” (“below”) interface 133a-133e, command/address (CA) interface 135a-135e, at least one memory array 136a-136e, availability circuitry 137a-137e, control circuitry 139a-139e, data through-silicon vias (TSVs) 141a-141e, and parity TSVs 142a-142e. Availability circuitry 137a-137e each respectively include parity circuitry 138a-138e. Control circuitry 139a-139e each respectively include mode circuitry 134a-134e. Controller 120 and memory integrated circuit die 130a-130e are integrated circuit type devices, such as those commonly referred to as “chips”. A memory controller, such as controller 120, manages the flow of data going to and from memory devices. Functionality of a memory controller may be included on a single die with a microprocessor, or included as part of a more complex integrated circuit system as a block of a system on a chip (SOC).