US-20260127106-A1 - MEMORY SYSTEM AND OPERATING METHOD OF THE SAME

Abstract

A memory system includes: a memory device including a plurality of memory blocks, and a controller configured to manage the plurality of memory blocks as N block groups, wherein the controller comprises: N operation cores, each configured to manage access to a corresponding block group by mapping a corresponding one of N physical address ranges corresponding to the N block groups to a corresponding one of N first logical address ranges, and a control core configured to manage a second logical address range shared with a host by dividing the second logical address range into N third logical address ranges that are sequential, and to manage access to the N operation cores by dynamically mapping the N third logical address ranges to the N first logical address ranges.

Inventors

• Duck Joo Lee
• Dong Wook Kim
• Min Cheol Kwon
• DAE HOON JANG

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260507

Application Date

20250401

Priority Date

20241105

Claims (20)

1. 1 . A memory system comprising: a memory device including a plurality of memory blocks; and a controller configured to manage the plurality of memory blocks as N block groups, wherein the controller comprises: N operation cores, each configured to manage access to a corresponding block group by mapping a corresponding one of N physical address ranges corresponding to the N block groups to a corresponding one of N first logical address ranges; and a control core configured to manage a second logical address range shared with a host by dividing the second logical address range into N third logical address ranges that are sequential, and to manage access to the N operation cores by dynamically mapping the N third logical address ranges to the N first logical address ranges, wherein N is a natural number equal to or greater than 2 .
2. 2 . The memory system of claim 1 , wherein the controller further comprises: N first mapping tables corresponding to the N operation cores, respectively, and a second mapping table corresponding to the control core.
3. 3 . The memory system of claim 2 , wherein each of the N operation cores manages a corresponding physical address range from among the N physical address ranges and a corresponding first logical address range from among the N first logical address ranges, in a corresponding first mapping table from among the N first mapping tables, by mapping the corresponding physical address range to the corresponding first logical address range.
4. 4 . The memory system of claim 3 , wherein each of the N operation cores controls at least one of a background operation or a journaling operation within a corresponding block group from among the N block groups, with reference to a corresponding first mapping table from among the N first mapping tables.
5. 5 . The memory system of claim 4 , wherein: each of the N operation cores generates a corresponding piece of state information by accumulating an operation state of a corresponding block group from among the N block groups, and the control core checks N pieces of state information at each set cycle and manages the N third logical address ranges and the N first logical address ranges in the second mapping table by dynamically mapping the N third logical address ranges to the N first logical address ranges based on results of the checking.
6. 6 . The memory system of claim 5 , wherein each of the N operation cores generates the corresponding piece of state information by accumulating an error rate occurring after a start of an access operation for the corresponding block group as the operation state of the corresponding block group.
7. 7 . The memory system of claim 5 , wherein each of the N operation cores generates the corresponding piece of state information by accumulating types and number of background operations performed in the corresponding block group as the operation state of the corresponding block group.
8. 8 . The memory system of claim 1 , wherein the memory device further comprises: a plurality of memory dies respectively corresponding to a plurality of channels through which data are input and output in an interleaving manner, each memory die comprising a plurality of planes, wherein the plurality of planes respectively correspond to a plurality of ways through which data are input and output in an interleaving manner by sharing a channel, each plane including multiple memory blocks.
9. 9 . The memory system of claim 8 , wherein the controller is configured to: group, as a super-memory block, a memory block from a first plane of a memory die with a memory block from a second plane of the memory die; and manage at least one super-memory block by including the at least one super-memory block in each of the N block groups.
10. 10 . The memory system of claim 8 , wherein the controller is configured to: group, as a super-memory block, a memory block from a first plane of a first memory die and a memory block from a first plane of a second memory die; group, as a super-memory block, a memory block from a second plane of the first memory die and a memory block from a second plane of the second memory die; and manage at least one super-memory block by including the at least one super-memory block in each of the N block groups.
11. 11 . The memory system of claim 8 , wherein the controller is configured to: group, as a super-memory block, a memory block from a first plane of a first memory die, a memory block from a second plane of the first memory die, a memory block from a first plane of a second memory die, and a memory block from a second plane of the second memory die; and manage at least one super-memory block by including the at least one super-memory block in each of the N block groups.
12. 12 . An operating method of a memory system, the memory system comprising a memory device including a plurality of memory blocks and a controller configured to manage the plurality of memory blocks as N block groups, wherein the controller includes a control core corresponding to a host and N operation cores respectively corresponding to the N block groups, the operating method comprising: managing, by each of the N operation cores, access to a corresponding one of the N block groups using a corresponding one of N first mapping tables that stores mappings between a corresponding one of N physical address ranges corresponding to the N block groups and a corresponding one of N first logical address ranges; managing, by the control core, a second logical address range shared with a host by dividing the second logical address range into N third logical address ranges that are sequential; managing, by the control core, access to each of the N operation cores using a second mapping table that stores mappings between the N third logical address ranges and the N first logical address ranges, wherein the mappings are dynamically updated, wherein N is a natural number equal to or greater than 2 .
13. 13 . The operating method of claim 12 , further comprising controlling, by each of the N operation cores, at least one of a background operation or a journaling operation within a corresponding block group from among the N block groups, with reference to a corresponding first mapping table from among the N first mapping tables.
14. 14 . The operating method of claim 13 , further comprising: generating, by each of the N operation cores, a corresponding piece of state information by accumulating an operation state of the corresponding block group, and checking N pieces of state information at each set cycle and managing the N third logical address ranges and the N first logical address ranges in the second mapping table by dynamically mapping the N third logical address ranges to the N first logical address ranges based on results of the checking, by the control core.
15. 15 . The operating method of claim 14 , further comprising generating, by each of the N operation cores, the corresponding piece of state information by accumulating an error rate occurring after a start of an access operation for the corresponding block group as the operation state of the corresponding block group.
16. 16 . The operating method of claim 14 , further comprising generating, by each of the N operation cores, the corresponding piece of state information by accumulating types and number of background operations performed in the corresponding block group as the operation state of the corresponding block group.
17. 17 . The operating method of claim 12 , wherein the memory device further comprises: a plurality of memory dies respectively corresponding to a plurality of channels through which data are input and output in an interleaving manner, each memory die comprising a plurality of planes, wherein the plurality of planes respectively correspond to a plurality of ways through which data are input and output in an interleaving manner by sharing a channel, each plane including multiple memory blocks.
18. 18 . The operating method of claim 17 , further comprising: grouping, as a super-memory block, a memory block from a first plane of a memory die and a memory block from a second plane of the memory die; and managing at least one super-memory block by including the at least one super-memory block in each of the N block groups.
19. 19 . The operating method of claim 17 , further comprising: grouping, as a super-memory block, a memory block from a first plane of a first memory die and a memory block from a first plane of a second memory die; grouping, as a super-memory block, a memory block from a second plane of the first memory die and a memory block from a second plane of the second memory die; and managing at least one super-memory block by including the at least one super-memory block in each of the N block groups.
20. 20 . The operating method of claim 17 , further comprising: grouping, as a super-memory block, a memory block from a first plane of a first memory die, a memory block from a second plane of the first memory die, a memory block from a first plane of a second memory die, and a memory block from a second plane of the second memory die; and managing at least one super-memory block by including the at least one super-memory block in each of the N block groups.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2024-0155084, filed in the Korean Intellectual Property Office on Nov. 5, 2024, the entire contents of which are incorporated herein by reference. BACKGROUND 1. Field Exemplary embodiments relate to a memory system, and more particularly, to a memory system that efficiently supports a flexible data placement (FDP) function and an operating method of the memory system. 2. Discussion of the Related Art Recently, a computer environment paradigm has shifted toward ubiquitous computing, which enables a computer system to be accessed anytime and everywhere. As a result, the use of portable electronic devices, such as mobile phones, digital cameras, notebook computers, and the like, has increased. Such portable electronic devices typically incorporate a memory system that includes at least one memory device as a data storage device. The data storage device may function as either a main storage device or an auxiliary storage device within the portable electronic device. A Nonvolatile Memory Device Retains Stored Data Even When the power supply is interrupted. Representative examples of the nonvolatile memory device include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase-change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. In a computing device, a data storage device implemented as a nonvolatile semiconductor memory device offers several advantages over a hard disk. Unlike a hard disk, it has no mechanical driving part (e.g., a mechanical arm), resulting in enhanced stability and durability. Additionally, it provides high data access speed and low power consumption. Examples of such a data storage device include a universal serial bus (USB) memory device, a memory card having various interfaces, and a solid state drive (SSD). A user of a memory system wants to efficiently and flexibly store as much data as needed through a flexible data placement (FDP) function, and to organize the data in a specific way. However, for the memory system to support the FDP function, the storage space of the memory system must be divided and managed across a plurality of cores. This division may result in an increase in the size of mapping information, which could lead to a rebuilding time when an error occurs. SUMMARY Various embodiments are directed to a memory system that efficiently supports an FDP function through a multi-stage mapping operation and to an operating method of the memory system. The problems addressed by the present disclosure are not limited to that mentioned above; additional unmentioned problems will be clearly understood by those skilled in the art from the following description. An aspect of an embodiment in the disclosure, a memory system may include: a memory device including a plurality of memory blocks; and a controller configured to manage the plurality of memory blocks as N block groups, wherein the controller may include: N operation cores, each configured to manage access to a corresponding block group by mapping a corresponding one of N physical address ranges corresponding to the N block groups to a corresponding one of N first logical address ranges; and a control core configured to manage a second logical address range shared with a host by dividing the second logical address range into N third logical address ranges that are sequential, and to manage access to the N operation cores by dynamically mapping the N third logical address ranges to the N first logical address ranges, wherein N may be a natural number equal to or greater than 2. An aspect of an embodiment in the disclosure, an operating method of a memory system, the memory system comprising a memory device including a plurality of memory blocks and a controller configured to manage the plurality of memory blocks as N block groups, wherein the controller includes a control core corresponding to a host and N operation cores respectively corresponding to the N block groups, the operating method may include: managing, by each of the N operation cores, access to a corresponding one of the N block groups using a corresponding one of N first mapping tables that stores mappings between a corresponding one of N physical address ranges corresponding to the N block groups and a corresponding one of N first logical address ranges; managing, by the control core, a second logical address range shared with a host by dividing the second logical address range into N third logical address ranges that are sequential; managing, by the control core, access to each of the N operation cores using a second mapping table that stores mappings between the N third logical address ranges and the N first logical address ranges, wherein the mappings are dy