US-20260127110-A1 - STORAGE DEVICE AND METHOD OF OPERATING STORAGE DEVICE

US20260127110A1US 20260127110 A1US20260127110 A1US 20260127110A1US-20260127110-A1

Abstract

A storage device includes a memory device and a memory controller to control the memory device by communicating with the memory device through a channel. The memory device includes a plurality of memory chips sharing the channel and each of the plurality of memory chips includes a transmission driver and an adaptive body bias generator. A target memory chip selected by the memory controller, among the plurality of memory chips, includes a first adaptive body bias generator and a first transmission driver. The first adaptive body bias generator applies a first body bias to the first transmission driver in a write mode in which the target memory chip receives a write data from the memory controller and applies a second body bias in a read mode in which the target memory chip transmits a read data to the memory controller.

Inventors

YoungHoon SON
JinHo Ryu
KYOUNGTAE KANG
Sangyun KIM
Jindo BYUN
Youngdon CHOI

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250826
Priority Date: 20241106

Claims (20)

1 . A storage device comprising: a memory device; and a memory controller configured to control the memory device through a channel, wherein the memory device includes a plurality of memory chips sharing the channel, the memory device being configured to select a target memory chip among the plurality of memory chips, wherein the target memory chip includes a first adaptive body bias generator and a first transmission driver, wherein the first adaptive body bias generator is configured to apply a first body bias to the first transmission driver based on an operation mode, the operation mode including a write mode or a read mode, and wherein the target memory chip is configured to receive a write data from the memory controller in the write mode and transmit a read data to the memory controller in the read mode.
2 . The storage device of claim 1 , wherein the first adaptive body bias generator is configured to: apply a reverse body bias to the first transmission driver in the write mode; and apply a normal body bias to the first transmission driver in the read mode.
3 . The storage device of claim 1 , wherein the first transmission driver includes a first n-type metal-oxide semiconductor (NMOS) transistor and a first p-type metal-oxide semiconductor (PMOS) transistor, wherein the first NMOS transistor and the first PMOS transistor are connected to a data transmission line that is included in the channel, and wherein the data transmission line is configured to transfer the read data and receive the write data.
4 . The storage device of claim 3 , wherein the first adaptive body bias generator is configured to apply, in the write mode, a reverse body bias to the first transmission driver by: applying a first bias voltage smaller than a ground voltage to a body of the first NMOS transistor; and applying a second bias voltage greater than a power supply voltage to a body of the first PMOS transistor.
5 . The storage device of claim 3 , wherein the first adaptive body bias generator is configured to apply, in the read mode, a normal body bias to the first transmission driver by: applying a first bias voltage corresponding to a ground voltage to a body of the first NMOS transistor; and applying a second bias voltage of a power supply voltage to a body of the first PMOS transistor.
6 . The storage device of claim 3 , wherein each of one or more non-target memory chips unselected by the memory controller, among the plurality of memory chips, includes an on-die termination (ODT) circuit connected to the data transmission line, wherein each of the one or more non-target memory chips includes a corresponding adaptive body bias generator and a corresponding transmission driver, and wherein the corresponding adaptive body bias generator is configured to apply a second body bias to the corresponding transmission driver based on a corresponding ODT circuit being enabled.
7 . The storage device of claim 6 , wherein the one or more non-target memory chips include a first non-target memory chip including a first ODT circuit that is enabled and a second non-target memory chip including a second ODT circuit that is disabled, wherein the first non-target memory chip includes a second adaptive body bias generator and a second transmission driver, and wherein the second non-target memory chip includes a third adaptive body bias generator and a third transmission driver.
8 . The storage device of claim 7 , wherein the second adaptive body bias generator is configured to apply a normal body bias to the second transmission driver, and wherein the third adaptive body bias generator is configured to apply a reverse body bias to the third transmission driver.
9 . The storage device of claim 8 , wherein the third transmission driver includes a second NMOS transistor and a second PMOS transistor, wherein the second NMOS transistor and the second PMOS transistor are connected to the data transmission line, and wherein the third adaptive body bias generator is configured to apply the reverse body bias to the third transmission driver by: applying a first bias voltage smaller than a ground voltage to a body of the second NMOS transistor; and applying a second bias voltage greater than a power voltage to a body of the second PMOS transistor.
10 . The storage device of claim 8 , wherein the second transmission driver includes a second NMOS transistor and a second PMOS transistor, wherein the second NMOS transistor and the second PMOS transistor are connected to the data transmission line, and wherein the second adaptive body bias generator is configured to apply the normal body bias to the second transmission driver by: applying a first bias voltage corresponding to a ground voltage to a body of the second NMOS transistor; and applying a second bias voltage of a power supply voltage to a body of the second PMOS transistor.
11 . The storage device of claim 6 , wherein each of the one or more non-target memory chips determines that a corresponding ODT circuit is enabled based on an ODT signal received from the memory controller, and wherein the corresponding ODT circuit is included in a corresponding transmission driver of each of the one or more non-target memory chips.
12 . The storage device of claim 1 , wherein each of the plurality of memory chips includes: a memory cell array including a plurality of nonvolatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines, the memory cell array configured to store the write data and provide the read data; an on-die termination (ODT) circuit connected to a data transmission line configured to transfer the read data and receive the write data, the data transmission line being included in the channel; and a control circuit configured to control a corresponding body bias generator based on a command and an address received from the memory controller and control the ODT circuit based on an ODT signal received from the memory controller, and wherein the plurality of memory chips are sequentially stacked on a printed circuit board in a direction vertical to a surface of the printed circuit board.
13 . The storage device of claim 12 , wherein the control circuit includes: an address comparator configured to generate an internal chip enable signal designating the target memory chip by comparing a chip address included in the address with an identifier address identifying each of the plurality of memory chips; and a control signal generator configured to generate an ODT control signal that selectively enables the ODT circuit based on the ODT signal.
14 . The storage device of claim 13 , wherein the address comparator is configured to: activate the internal chip enable signal based on the chip address matching the identifier address; and deactivate the internal chip enable signal based on the chip address being different from the identifier address.
15 . The storage device of claim 12 , wherein the plurality of memory chips are configured to operate in a chip enable reduction mode in which the plurality of memory chips commonly receive a chip enable signal and a chip address.
16 . The storage device of claim 12 , wherein the control circuit is configured to: selectively activate an internal chip enable signal designating the target memory chip based on a command/address chip enable signal and a command/address received from the memory controller; and generate an ODT control signal that selectively enables the ODT circuit based on the ODT signal, and wherein the command/address includes a logical unit number (LUN) address indicating an active LUN.
17 . A storage device comprising: a memory device; and a memory controller configured to control the memory device through a channel and to select a target memory chip among a plurality of memory chips, wherein the memory device includes the plurality of memory chips sharing a data bus that transfers data and receiving respective chip selection signals from the memory controller, wherein each of the plurality of memory chips includes a memory cell array, a transmission driver and an adaptive body bias generator, the memory cell array including a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines, the memory cell array configured to store the data, wherein the target memory chip includes a first adaptive body bias generator and a first transmission driver, and wherein the first adaptive body bias generator is configured to apply a first body bias to the first transmission driver based on an operation mode, the operation mode including a write mode or a read mode, and wherein the target memory chip is configured to receive a write data from the memory controller in the write mode and transmit a read data to the memory controller in the read mode.
18 . The storage device of claim 17 , wherein the first adaptive body bias generator is configured to: apply a reverse body bias to the first transmission driver in the write mode; and apply a normal body bias to the first transmission driver in the read mode, wherein the first transmission driver includes a first n-type metal-oxide semiconductor (NMOS) transistor and a first p-type metal-oxide semiconductor (PMOS) transistor that are connected to the data bus, wherein the first adaptive body bias generator is configured to apply, in the write mode, the reverse body bias to the first transmission driver by: applying a first bias voltage smaller than a ground voltage to a body of the first NMOS transistor; and applying a second bias voltage greater than a power voltage to a body of the first PMOS transistor, and wherein the first adaptive body bias generator is configured to apply, in the read mode, the normal body bias to the first transmission driver by: applying the first bias voltage corresponding to the ground voltage to the body of the first NMOS transistor; and applying the second bias voltage of a power supply voltage to the body of the first PMOS transistor.
19 . The storage device of claim 17 , wherein each of one or more non-target memory chips unselected by the memory controller, among the plurality of memory chips, includes an on-die termination (ODT) circuit connected to a data transmission line, wherein each of the one or more non-target memory chips includes a corresponding adaptive body bias generator and a corresponding transmission driver, wherein the corresponding adaptive body bias generator is configured to apply a second body bias to the corresponding transmission driver based on a corresponding ODT circuit being enabled, wherein the one or more non-target memory chips include a first non-target memory chip including a first ODT circuit that is enabled and a second non-target memory chip including a second ODT circuit that is disabled, wherein the first non-target memory chip includes a second adaptive body bias generator and a second transmission driver, wherein the second non-target memory chip includes a third adaptive body bias generator and a third transmission driver, wherein the second adaptive body bias generator is configured to apply a normal body bias to the second transmission driver, and wherein the third adaptive body bias generator is configured to apply a reverse body bias to the third transmission driver.
20 . A method of operating a storage device, wherein the storage device includes a memory device and a memory controller configured to control the memory device by communicating with the memory device through a channel, and wherein the memory device includes a plurality of memory chips sharing the channel, the method comprising: determining that each of plurality of memory chips is selected as a target memory chip based on a chip address from the memory controller; applying, by a first adaptive body bias generator, a first body bias to a first transmission driver based on an operation mode being a write mode or a read mode, the first adaptive body bias generator and the first transmission driver being included in a first memory chip that is selected as the target memory chip by the memory controller, among the plurality of memory chips; and applying, by a second adaptive body bias generator, a second body bias to a second transmission driver based on that a corresponding on-die termination function is enabled, the second adaptive body bias generator and second transmission driver being included in each of one or more non-target memory chips except the first memory chip, among the plurality of memory chips.

Description

CROSS-REFERENCE TO RELATED APPLICATION This US application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2024-0155842, filed on Nov. 6, 2024, in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND A storage device may include a memory device including a plurality of memory chips and a controller to control the memory device. In related memory systems, signal communication between a memory device and a controller may perform at relatively low operating frequencies, as compared with signal communication in memory systems including high speed memory, such as dynamic random-access memory (DRAM) or static random-access memory (SRAM). As demand for high speed storage devices is rising, the integrity (or robustness) of signals communicated between the memory device and the controller and capacitance of input/output pads for reducing channel power become desired in the design and operation of storage device(s) in computing systems and/or mobile communication systems. SUMMARY Some example implementations may provide a storage device capable of reducing capacitance of input/output pads. Some example implementations may provide a method of operating a storage device, capable of reducing capacitance of input/output pads. According to some example implementations, a storage device includes a memory device and a memory controller to control the memory device through a channel. The memory device includes a plurality of memory chips sharing the channel and the memory device selects a target memory chip among the plurality of memory chips. The target memory chip includes a first adaptive body bias generator and a first transmission driver. The first adaptive body bias generator applies a first body bias to the first transmission driver based on an operation mode including a write mode or a read mode. In the write mode, the target memory chip receives a write data from the memory controller and in the read mode the target memory chip transmits a read data to the memory controller. According to some example implementations, a storage includes a memory device and a memory controller to control the memory device through a channel and selects a target memory chip among a plurality of memory chip. The memory device includes the plurality of memory chips sharing a data bus that transfers data and receiving respective chip selection signals from the memory controller. Each of the plurality of memory chips includes a memory cell array, a transmission driver and an adaptive body bias generator, the memory cell array includes a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines and the memory cell array stores the data. The target memory chip includes a first adaptive body bias generator and a first transmission driver. The first adaptive body bias generator applies a first body bias to the first transmission driver based on an operation mode including a write mode or a read mode. In the write mode, the target memory chip receives a write data from the memory controller and in the read mode the target memory chip transmits a read data to the memory controller. According to some example implementations, there is provided a method of operating a storage device. The storage device includes a memory device and a memory controller to control the memory device by communicating with the memory device through a channel, and the memory device includes a plurality of memory chips sharing the channel. According to the method, that in each of plurality of memory chips is selected as a target memory chip based on a chip address from the memory controller is determined, a first body bias is applied, by a first adaptive body bias generator, to a first transmission driver based on an operation mode being a write mode or a read mode, where the first adaptive body bias generator and the first transmission driver being is included in a first memory chip that is selected as the target memory chip by the memory controller, among the plurality of memory chips, and a second body bias is applied, by a second adaptive body bias generator, to a second transmission driver based on that a corresponding on-die termination function is enabled, where the second adaptive body bias generator and second transmission driver is included in each of one or more non-target memory chips except the first memory chip, among the plurality of memory chips. Accordingly, in the storage device and the mothed of operating the storage device according to example implementations, an adaptive body bias generator in a selected chip may apply different body bias to a corresponding transmission driver based on an operation mode and an adaptive body bias generator in an unselected chip may apply different body bias to a corresponding transmission driver based on whether an on-die termination (ODT) function is enabled. Therefore, the