US-20260127112-A1 - WRITE COMMAND TIMING ENHANCEMENT

Abstract

Methods, systems, and devices for write command timing enhancement are described. A host device may transmit (e.g., issue), to a memory device, an activation command and an associated write command according to a delay that is different (e.g., shorter) than a row access to column access delay associated with read commands. In some examples, the delay between the activation command and the associated write command may be a function of the row access to column access delay associated with read commands and one or more additional parameters, such as a timing constraint or a speed parameter of the memory device.

Inventors

• Sujeet V. Ayyapureddi
• Scott E. Smith
• Matthew A. Prather
• Erik V. Pohlmann

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260507

Application Date

20251219

Claims (20)

1. 1 . A method, comprising: reading, at a memory device, a memory cell based at least in part on receiving a write command, wherein the write command is received an amount of time after reception of an activation command and the amount of time is based at least in part on a function of a row address to column address delay, associated with the memory device, and one or more additional parameters; determining that a quantity of memory cells to be written in response to the write command is less than a quantity of memory cells for an error detection operation; determining, in accordance with the error detection operation and based at least in part on reading the memory cell, that a prior logic state written to the memory cell includes an error; correcting the error using an error correction procedure based at least in part on determining that the prior logic state includes the error; and writing a logic state to the memory cell based at least in part on correcting the error.
2. 2 . The method of claim 1 , wherein the one or more additional parameters comprise: a command delay, a recovery time, a speed parameter, or a predetermined parameter.
3. 3 . The method of claim 2 , wherein the command delay is a row activation command delay or a column activation command delay.
4. 4 . The method of claim 2 , wherein the recovery time is a write recovery time.
5. 5 . The method of claim 2 , wherein the speed parameter is a speed grade of the memory device.
6. 6 . The method of claim 1 , wherein reading the memory cell and correcting the error are based at least in part on performing a read-modify-write operation.
7. 7 . The method of claim 6 , wherein the read-modify-write operation is triggered for each write command based at least in part on a quantity of columns accessed for access operations and based at least in part on a data bus width of the memory device.
8. 8 . The method of claim 6 , wherein the read-modify-write operation is triggered by the write command having a partial pit set to low.
9. 9 . The method of claim 1 , wherein the amount of time is based at least in part on subtracting a second amount of time from the row address to column address delay.
10. 10 . The method of claim 1 , wherein read commands associated with the memory device are received at least a second amount of time after receiving activation commands associated with the memory device, the second amount of time corresponding to the row address to column address delay.
11. 11 . The method of claim 1 , wherein the amount of time comprises a quantity of clock cycles.
12. 12 . An apparatus, comprising: processing circuitry associated with a memory device and configured to cause the apparatus to: read a memory cell based at least in part on receiving a write command, wherein the write command is received an amount of time after reception of an activation command and the amount of time is based at least in part on a function of a row address to column address delay, associated with the memory device, and one or more additional parameters; determine that a quantity of memory cells to be written in response to the write command is less than a quantity of memory cells for an error detection operation; determine, in accordance with the error detection operation and based at least in part on reading the memory cell, that a prior logic state written to the memory cell includes an error; correct the error using an error correction procedure based at least in part on determining that the prior logic state includes the error; and write a logic state to the memory cell based at least in part on correcting the error.
13. 13 . The apparatus of claim 12 , wherein the one or more additional parameters comprise: a command delay, a recovery time, a speed parameter, or a predetermined parameter.
14. 14 . The apparatus of claim 12 , wherein reading the memory cell and correcting the error are based at least in part on performing a read-modify-write operation.
15. 15 . The apparatus of claim 14 , wherein the read-modify-write operation is triggered for each write command based at least in part on a quantity of columns accessed for access operations and based at least in part on a data bus width of the memory device.
16. 16 . The apparatus of claim 14 , wherein the read-modify-write operation is triggered by the write command having a partial pit set to low.
17. 17 . The apparatus of claim 12 , wherein the amount of time is based at least in part on subtracting a second amount of time from the row address to column address delay.
18. 18 . A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to: read, at a memory device, a memory cell based at least in part on receiving a write command, wherein the write command is received an amount of time after reception of an activation command and the amount of time is based at least in part on a function of a row address to column address delay, associated with the memory device, and one or more additional parameters; determine that a quantity of memory cells to be written in response to the write command is less than a quantity of memory cells for an error detection operation; determine, in accordance with the error detection operation and based at least in part on reading the memory cell, that a prior logic state written to the memory cell includes an error; correct the error using an error correction procedure based at least in part on determining that the prior logic state includes the error; and write a logic state to the memory cell based at least in part on correcting the error.
19. 19 . The non-transitory computer-readable medium of claim 18 , wherein reading the memory cell and correcting the error are based at least in part on performing a read-modify-write operation.
20. 20 . The non-transitory computer-readable medium of claim 19 , wherein: the read-modify-write operation is triggered for each write command based at least in part on a quantity of columns accessed for access operations and based at least in part on a data bus width of the memory device, or the read-modify-write operation is triggered by the write command having a partial pit set to low.

Description

CROSS REFERENCE The present Application for Patent is a continuation of U.S. Patent Application No. 18/144,655 by Ayyapureddi et al., entitled “WRITE COMMAND TIMING ENHANCEMENT,” filed May 8, 2023, which claims priority to U.S. Provisional Patent Application No. 63/364,545 by Ayyapureddi et al., entitled “WRITE COMMAND TIMING ENHANCEMENT,” filed May 11, 2022, each of which is assigned to the assignee hereof, and each of which is expressly incorporated by reference herein. FIELD OF TECHNOLOGY The following relates to one or more systems for memory, including write command timing enhancement. BACKGROUND Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, a component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) a stored state in the memory device. To store information, a component may write (e.g., program, set, assign) the state in the memory device. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of a system that supports write command timing enhancement in accordance with examples as disclosed herein. FIG. 2 illustrates an example of a memory die that supports write command timing enhancement in accordance with examples as disclosed herein. FIG. 3 illustrates an example of a memory system that supports write command timing enhancement in accordance with examples as disclosed herein. FIG. 4 illustrates an example of a command timeline that supports write command timing enhancement in accordance with examples as disclosed herein. FIG. 5 shows a block diagram of a memory device that supports write command timing enhancement in accordance with examples as disclosed herein. FIG. 6 shows a block diagram of a host device that supports write command timing enhancement in accordance with examples as disclosed herein. FIGS. 7 and 8 show flowcharts illustrating a method or methods that support write command timing enhancement in accordance with examples as disclosed herein. DETAILED DESCRIPTION To access a memory cell within a memory device (e.g., a random access memory (RAM) device), separate operations may be performed which may be triggered by separate, corresponding commands (e.g., sent by a host device or a controller such as a controller of the host device) to the memory device. For example, the memory device may receive an activation command for a set (e.g., a row) of memory cells, which may trigger an activation operation. The activation operation may activate (e.g., open) the set of memory cells within the memory device. After the activation command, the memory device may receive a data access command (e.g., a read, a write, a program, a rewrite) directed to the activated set of memory cells. Based on the data access command, the memory device may read data from or write data to one or more memory cells of the activated set. Each of the steps of the memory access operations (e.g., activating, accessing) may have an associated latency. In some cases, the memory access operations may be subject to one or more configured memory timing constraints, for example according to an industry standard specification (e.g., a JEDEC DDR5 specification). A row access to column access delay (such as tRCD) may represent a duration between an activation command and an associated data access command, which may be based on a capability of a memory device. An activation command delay, such as a row activation delay (e.g., a row-to-row activation delay (such as tRRD)) or a column activation delay (e.g., a column-to-column activation delay (such as tCCD)), may be a duration between consecutive activation commands. In some examples, such as when a host device transmits (e.g., issues) consecutive activation commands