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US-20260127118-A1 - ADAPTIVE STEP DELAY IN PERIPHERAL TRIGGER GENERATOR

US20260127118A1US 20260127118 A1US20260127118 A1US 20260127118A1US-20260127118-A1

Abstract

A Peripheral Trigger Generator (PTG) for generating signals adaptively responsive to time-driven events based on execution run time. A variable PTG step delay, such as a “wait for software trigger” command, may provide an adaptive step delay between the output trigger commands. An adaptive step delay may use a combination of PTG Command+Control Bit in PTG Special Function Register. The adaptive step delay may be part of the Functional Safety Diagnostics package developed for the PTG module.

Inventors

  • Avinash Halageri
  • Swathi G. Bhat

Assignees

  • MICROCHIP TECHNOLOGY INCORPORATED

Dates

Publication Date
20260507
Application Date
20241107
Priority Date
20241101

Claims (20)

  1. 1 . A microcontroller comprising: a central processing unit (CPU); a plurality of peripheral units coupled with said CPU; and a peripheral trigger generator and operating independently from the CPU and being coupled with the plurality of peripheral units, wherein the peripheral trigger generator comprises a state machine which is programmable via said CPU by a plurality of sequential programming steps, wherein a variable step delay command is interleaved with at least one output trigger command, wherein the peripheral trigger generator is configured to receive a plurality of input signals and depending on a programming of the state machine selects at least one of said plurality of input signals and independent from the CPU controls a function of a selected one of said plurality of peripheral units depending on the selected input signal and the programming of the state machine, wherein the state machine generates at least one output signal to control the function of the selected peripheral unit.
  2. 2 . The microcontroller according to claim 1 , wherein the state machine of the peripheral trigger generator comprises control logic receiving said selected input signal, a programmable step queue controlled by said control logic and comprising a plurality of registers storing said sequential programming steps and a command decoder coupled with the control logic and operable to receive the sequential programming steps and to generate the at least one output signal.
  3. 3 . The microcontroller according to claim 1 , wherein the at least one output signal is a trigger signal that controls one of said peripheral units independently from said CPU.
  4. 4 . The microcontroller according to claim 3 , wherein said one peripheral unit is an analog-to-digital converter.
  5. 5 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that causes the peripheral trigger generator to wait for a variable step delay trigger condition of a selected input signal and to execute a following programming step said selected input signal meets the variable step delay trigger condition.
  6. 6 . The microcontroller according to claim 5 , wherein the variable step delay trigger condition is a bit transition from 0 to 1.
  7. 7 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that causes the peripheral trigger generator before executing a following programming step to wait for a variable step delay trigger condition.
  8. 8 . The microcontroller according to claim 7 , wherein the variable step delay trigger is provided by setting a bit by the CPU in a control register of the peripheral trigger generator.
  9. 9 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that generates an interrupt signal fed to said CPU.
  10. 10 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that jumps to another programming step when a condition is fulfilled.
  11. 11 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that generates said at least one output signal.
  12. 12 . The microcontroller according to claim 1 , wherein the sequential programming steps allow for a coding that broadcasts a plurality of output signals.
  13. 13 . The microcontroller according to claim 1 , wherein each programming step of the sequential programming steps comprises a command code and a parameter code.
  14. 14 . The microcontroller according to claim 1 , further comprising a watchdog timer wherein the watchdog timer is reset after completion of a programming step and a timeout of the watchdog timer stops execution of the sequential programming steps.
  15. 15 . The microcontroller according to claim 14 , wherein a timeout of the watchdog timer is programmable.
  16. 16 . The microcontroller according to claim 14 , wherein a timeout of the watchdog timer generates an interrupt fed to the CPU.
  17. 17 . The microcontroller according to claim 1 , wherein the peripheral trigger generator is configured to generate a plurality of output signals for a predefined number of peripheral units, wherein each output signal is generated upon execution of a programming step.
  18. 18 . The microcontroller according to claim 1 , wherein the peripheral trigger generator is configured to further generate a strobed output signal upon execution of a programming step, wherein the strobed output signal comprises a plurality of parallel output signals.
  19. 19 . The microcontroller according to claim 18 , wherein a value of the strobed output signal is provided by a parameter coded within the programming step.
  20. 20 . The microcontroller according to claim 19 , wherein the value has n bits and is extended to a bit width being greater than n.

Description

RELATED PATENT APPLICATION This application claims priority to commonly owned Indian Patent Application number 202411083757 filed Nov. 1, 2024, the entire contents of which are hereby incorporated by reference for all purposes. TECHNICAL FIELD The present disclosure relates to a peripheral trigger generator, in particular, for use in a microcontroller. BACKGROUND Systems and methods can be provided to generate accurate and complex sequences of signals within a microcontroller to trigger, for example, an ADC (Analog Digital Converter) module to sample and convert analog signals in an application circuit. Using typical software methods is generally too imprecise and requires too much processor overhead. A peripheral trigger generator (PTG) allows, without CPU intervention, events that occur in a peripheral to (1) conditionally generate trigger(s) in another peripheral that vary in time and frequency; and (2) reconfigure the operation of another peripheral (e.g. ATD input channel select). A Peripheral Trigger Generator (PTG) is user programmable via a PTG assembly language. The PTG may operate independently of the processor. The PTG can monitor selected peripheral signaling and generate signaling to other peripherals and/or the processor. The PTG can provide timing accuracy not possible if implemented in software. The PTG may operate faster than the CPU. Consequently, the PTG can monitor a number of inputs and generate complex timing sequences with a time accuracy not possible via software. Synchronization between a CPU execution flow and PTG execution flow is achieved using a “PTG step delay.” The PTG Step Delay is a precomputed delay and can be computed taking into account the execution time of one peripheral. “Run time computation” of the Step delay is not possible, so the same PTG Step delay is used before triggering the subsequent peripheral, which may be less or more than what is required for the subsequent peripheral. Other commands are available to change the PTG Step delay, i.e., provide a variable step delay, but those commands are precomputed and have limited capabilities. The PTG step delay can be computed only once. If multiple peripherals are triggered using the output trigger, the step delay can be computed in relation to execution time of only one peripheral. Variation in execution time of target peripherals causes a cascading effect and subsequent peripherals may miss triggers. There is a need for a Peripheral Trigger Generator (PTG) for generating signals adaptively responsive to time-driven events based on execution run time. SUMMARY Aspects provide a Peripheral Trigger Generator (PTG) for generating signals adaptively responsive to time-driven events based on execution run time. The PTG Step delay may be replaced with a “wait for software trigger” command to provide an adaptive step delay between the output trigger commands. A software algorithm may introduce an adaptive step delay in a PTG module. An adaptive step delay may use a combination of PTG Command+Control Bit in PTG Special Function Register. The adaptive step delay may be part of the Functional Safety Diagnostics package developed for the PTG module. The adaptive step delay may be used in diagnostics for PTG module in Automotive Domain applications. Aspects provide a microcontroller comprising: a central processing unit (CPU); a plurality of peripheral units coupled with said CPU; and a peripheral trigger generator and operating independently from the CPU and being coupled with the plurality of peripheral units, wherein the peripheral trigger generator comprises a state machine which is programmable via said CPU by a plurality of sequential programming steps, wherein a variable step delay command is interleaved with at least one output trigger command, wherein the peripheral trigger generator is configured to receive a plurality of input signals and depending on a programming of the state machine selects at least one of said plurality of input signals and independent from the CPU controls a function of a selected one of said plurality of peripheral units depending on the selected input signal and the programming of the state machine, wherein the state machine generates at least one output signal to control the function of the selected peripheral unit. An aspect provides a microcontroller as in the previous paragraph, wherein the state machine of the peripheral trigger generator comprises control logic receiving said selected input signal, a programmable step queue controlled by said control logic and comprising a plurality of registers storing said sequential programming steps and a command decoder coupled with the control logic and operable to receive the sequential programming steps and to generate the at least one output signal. An aspect provides a microcontroller as in one of the previous two paragraphs, wherein the at least one output signal is a trigger signal that controls one of said peripheral units independently from s